This is an automated email from Gerrit.
Kent Brinkley (jkbrinkley.img...@gmail.com) just uploaded a new patch set to
Gerrit, which you can find at http://openocd.zylin.com/2413
-- gerrit
commit 855a8f9c7415621724d9cee815171b69494402a3
Author: Kent Brinkley <jkbrinkley.img...@gmail.com>
Date: Tue Nov 25 16:10:21 2014 -0700
Added support the MIPS microAptiv Core
Added support the MIPS microAptic core. Both the
microController (uC) and microProcessor (uP) cores
are supported and testing has been done using PIC32MZ
Starter Kit from MicroChip (uP core). Tools used to
compile, link and gdb supplied by Mentor Graphics
(Sourcery_CodeBench_Lite_for_MIPS_ELF) and early
testing using Imagination Technologies Codescape MIPS
SDK
http://community.imgtec.com/developers/mips/tools/codescape-mips-sdk/
Probe used: BusBlaster v3c from Dangerous Prototypes.
Change-Id: Ib6945b2fbab1616bf5b4676d2f2d4a23f08e99c9
Signed-off-by: Kent Brinkley <jkbrinkley.img...@gmail.com>
Fixed Formatting issues
Fixed Formatting issues
Change-Id: I864ea9bf82c6367876a1f031ac7e007e08737a79
Signed-off-by: Kent Brinkley <jkbrinkley.img...@gmail.com>
Removed #ifdef code
Removed #ifdef code
Change-Id: Ieee7264ac6f12cf1664a8ff5b7e2644e3d20e7b6
Signed-off-by: Kent Brinkley <jkbrinkley.img...@gmail.com>
Fixed overlook patch format issues
Fixed overlook patch format issues
Change-Id: Ifca4633c6ac935862d602f200d72ad2b37463de5
Signed-off-by: Kent Brinkley <jkbrinkley.img...@gmail.com>
diff --git a/src/target/Makefile.am b/src/target/Makefile.am
index f47ebd4..63eed08 100644
--- a/src/target/Makefile.am
+++ b/src/target/Makefile.am
@@ -110,6 +110,7 @@ MIPS32_SRC = \
mips32.c \
mips_common.c \
mips_m4k.c \
+ mips_mAptiv.c \
mips32_pracc.c \
mips32_dmaacc.c \
mips_ejtag.c
@@ -171,6 +172,7 @@ noinst_HEADERS = \
mips32.h \
mips_common.h \
mips_m4k.h \
+ mips_mAptiv.h \
mips_ejtag.h \
mips32_pracc.h \
mips32_dmaacc.h \
diff --git a/src/target/mips32.c b/src/target/mips32.c
index d12368e..72301a0 100644
--- a/src/target/mips32.c
+++ b/src/target/mips32.c
@@ -198,11 +198,19 @@ int mips32_save_context(struct target *target)
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
/* read core registers */
- mips32_pracc_read_regs(ejtag_info, mips32->core_regs);
-
+ int retval = mips32_pracc_read_regs(ejtag_info, mips32->core_regs);
+ if (retval != ERROR_OK) {
+ LOG_DEBUG("mips32_pracc_read_regs failed");
+ return retval;
+ }
for (i = 0; i < MIPS32NUMCOREREGS; i++) {
- if (!mips32->core_cache->reg_list[i].valid)
- mips32->read_core_reg(target, i);
+ if (!mips32->core_cache->reg_list[i].valid) {
+ retval = mips32->read_core_reg(target, i);
+ if (retval != ERROR_OK) {
+ LOG_DEBUG("mips32->read_core_reg failed");
+ return retval;
+ }
+ }
}
return ERROR_OK;
@@ -230,6 +238,19 @@ int mips32_restore_context(struct target *target)
int mips32_arch_state(struct target *target)
{
struct mips32_common *mips32 = target_to_mips32(target);
+ struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
+ int retval;
+ uint32_t config3;
+ uint32_t cp0_reg = 16;
+ uint32_t cp0_sel = 3;
+ retval = mips32_cp0_read(ejtag_info, &config3, cp0_reg, cp0_sel);
+ if (retval != ERROR_OK) {
+ LOG_DEBUG("reading config3 register failed");
+ return retval;
+ }
+ mips32->dsp_implemented = ((config3 & CFG3_DSPP) >> 10);
+ mips32->dsp_rev = ((config3 & CFG3_DSP_REV) >> 11);
+ mips32->mmips = ((config3 & CFG3_ISA_MODE) >> 14);
LOG_USER("target halted in %s mode due to %s, pc: 0x%8.8" PRIx32 "",
mips_isa_strings[mips32->isa_mode],
@@ -297,7 +318,7 @@ int mips32_init_arch_info(struct target *target, struct
mips32_common *mips32, s
mips32->read_core_reg = mips32_read_core_reg;
mips32->write_core_reg = mips32_write_core_reg;
- mips32->ejtag_info.scan_delay = 2000000; /* Initial default
value */
+ mips32->ejtag_info.scan_delay = MIPS32_SCAN_DELAY_LEGACY_MODE; /*
Initial default value */
mips32->ejtag_info.mode = 0; /* Initial default
value */
return ERROR_OK;
@@ -562,14 +583,14 @@ int mips32_configure_break_unit(struct target *target)
}
/* check if target endianness settings matches debug control register */
- if (((ejtag_info->debug_caps & EJTAG_DCR_ENM)
- && (target->endianness == TARGET_LITTLE_ENDIAN)) ||
- (!(ejtag_info->debug_caps & EJTAG_DCR_ENM)
- && (target->endianness == TARGET_BIG_ENDIAN)))
+ if (((ejtag_info->debug_caps & EJTAG_DCR_ENM) && (target->endianness ==
TARGET_LITTLE_ENDIAN)) ||
+ (!(ejtag_info->debug_caps & EJTAG_DCR_ENM) &&
(target->endianness == TARGET_BIG_ENDIAN))) {
LOG_WARNING("DCR endianness settings does not match target
settings");
+ LOG_WARNING("Config file does not match DCR endianness - DCR:
0x%8.8x", ejtag_info->debug_caps);
+ }
LOG_DEBUG("DCR 0x%" PRIx32 " numinst %i numdata %i", dcr,
mips32->num_inst_bpoints,
- mips32->num_data_bpoints);
+ mips32->num_data_bpoints);
mips32->bp_scanned = 1;
@@ -886,25 +907,7 @@ COMMAND_HANDLER(mips32_handle_cp0_command)
COMMAND_HANDLER(mips32_handle_scan_delay_command)
{
- struct target *target = get_current_target(CMD_CTX);
- struct mips32_common *mips32 = target_to_mips32(target);
- struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
-
- if (CMD_ARGC == 1)
- COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], ejtag_info->scan_delay);
- else if (CMD_ARGC > 1)
- return ERROR_COMMAND_SYNTAX_ERROR;
-
- command_print(CMD_CTX, "scan delay: %d nsec", ejtag_info->scan_delay);
- if (ejtag_info->scan_delay >= 2000000) {
- ejtag_info->mode = 0;
- command_print(CMD_CTX, "running in legacy mode");
- } else {
- ejtag_info->mode = 1;
- command_print(CMD_CTX, "running in fast queued mode");
- }
-
- return ERROR_OK;
+ return mips32_scan_delay_command(cmd);
}
static const struct command_registration mips32_exec_command_handlers[] = {
@@ -915,7 +918,7 @@ static const struct command_registration
mips32_exec_command_handlers[] = {
.help = "display/modify cp0 register(s)",
.usage = "[[reg_name|regnum select] [value]]",
},
- {
+ {
.name = "scan_delay",
.handler = mips32_handle_scan_delay_command,
.mode = COMMAND_ANY,
diff --git a/src/target/mips32.h b/src/target/mips32.h
index 9bf9089..b0e9ef4 100644
--- a/src/target/mips32.h
+++ b/src/target/mips32.h
@@ -123,6 +123,23 @@ enum mips32_isa_mode {
MIPS32_ISA_MIPS16E = 1,
};
+enum micro_mips_enabled {
+ MIPS32_ONLY = 0,
+ MICRO_MIPS_ONLY = 1,
+ MICRO_MIPS32_16_ONRESET_MIPS32 = 2,
+ MICRO_MIPS32_16_ONRESET_MIPS16 = 3,
+};
+
+enum dsp {
+ DSP_NOT_IMP = 0,
+ DSP_IMP = 1,
+};
+
+enum dsp_rev {
+ DSP_REV1 = 0,
+ DSP_REV2 = 1,
+};
+
struct mips32_comparator {
int used;
uint32_t bp_value;
@@ -136,6 +153,9 @@ struct mips32_common {
struct mips_ejtag ejtag_info;
uint32_t core_regs[MIPS32NUMCOREREGS];
enum mips32_isa_mode isa_mode;
+ enum micro_mips_enabled mmips;
+ enum dsp dsp_implemented;
+ enum dsp_rev dsp_rev;
/* working area for fastdata access */
struct working_area *fast_data_area;
@@ -170,6 +190,22 @@ struct mips32_algorithm {
enum mips32_isa_mode isa_mode;
};
+/*
+ * MIPS32r2 Config3 Register (CP0 Register 16, Select 3)
+ */
+#define CFG3_M 0x80000000 /* Config4 implemented
*/
+#define CFG3_ISAONEXC 0x00010000 /* ISA mode on exception entry
*/
+#define CFG3_ISA_MODE 0x0000C000 /* ISA mode */
+#define CFG3_DSP_REV 0x00000800 /* DSP Rev */
+#define CFG3_DSPP 0x00000400 /* DSP ASE present */
+#define CFG3_LPA 0x00000080 /* Large physical
addresses */
+#define CFG3_VEIC 0x00000040 /* Vectored external
i/u controller */
+#define CFG3_VI 0x00000020 /* Vectored
i/us */
+#define CFG3_SP 0x00000010 /* Small page
support */
+#define CFG3_MT 0x00000004 /* MT ASE
present */
+#define CFG3_SM 0x00000002 /* SmartMIPS
ASE */
+#define CFG3_TL 0x00000001 /* Trace Logic
*/
+
#define MIPS32_OP_ADDIU 0x21
#define MIPS32_OP_ANDI 0x0C
#define MIPS32_OP_BEQ 0x04
@@ -179,6 +215,7 @@ struct mips32_algorithm {
#define MIPS32_OP_AND 0x24
#define MIPS32_OP_CACHE 0x2F
#define MIPS32_OP_COP0 0x10
+#define MIPS32_OP_EXT 0x1F
#define MIPS32_OP_J 0x02
#define MIPS32_OP_JR 0x08
#define MIPS32_OP_LUI 0x0F
@@ -188,6 +225,7 @@ struct mips32_algorithm {
#define MIPS32_OP_MFHI 0x10
#define MIPS32_OP_MTHI 0x11
#define MIPS32_OP_MFLO 0x12
+#define MIPS32_OP_MUL 0x2
#define MIPS32_OP_MTLO 0x13
#define MIPS32_OP_RDHWR 0x3B
#define MIPS32_OP_SB 0x28
@@ -197,6 +235,7 @@ struct mips32_algorithm {
#define MIPS32_OP_XORI 0x0E
#define MIPS32_OP_XOR 0x26
#define MIPS32_OP_SLTU 0x2B
+#define MIPS32_OP_SLLV 0x04
#define MIPS32_OP_SRL 0x03
#define MIPS32_OP_SYNCI 0x1F
@@ -216,7 +255,9 @@ struct mips32_algorithm {
#define MIPS32_J_INST(opcode, addr) (((opcode) << 26) | (addr))
#define MIPS32_NOP 0
+#define MIPS32_ADD(dst, src, tar) MIPS32_R_INST(0, src, tar, dst,
0, 32)
#define MIPS32_ADDI(tar, src, val) MIPS32_I_INST(MIPS32_OP_ADDI,
src, tar, val)
+#define MIPS32_ADDIU(tar, src, val) MIPS32_I_INST(9, src, tar, val)
#define MIPS32_ADDU(dst, src, tar)
MIPS32_R_INST(MIPS32_OP_SPECIAL, src, tar, dst, 0, MIPS32_OP_ADDIU)
#define MIPS32_AND(reg, off, val) MIPS32_R_INST(0, off, val, reg,
0, MIPS32_OP_AND)
#define MIPS32_ANDI(tar, src, val) MIPS32_I_INST(MIPS32_OP_ANDI,
src, tar, val)
@@ -225,9 +266,11 @@ struct mips32_algorithm {
#define MIPS32_BGTZ(reg, off) MIPS32_I_INST(MIPS32_OP_BGTZ,
reg, 0, off)
#define MIPS32_BNE(src, tar, off) MIPS32_I_INST(MIPS32_OP_BNE,
src, tar, off)
#define MIPS32_CACHE(op, off, base) MIPS32_I_INST(MIPS32_OP_CACHE,
base, op, off)
+#define MIPS32_EXT(dst, src, shf, sz) MIPS32_R_INST(MIPS32_OP_EXT, src, dst,
(sz-1), shf, 0)
#define MIPS32_J(tar) MIPS32_J_INST(MIPS32_OP_J, tar)
#define MIPS32_JR(reg) MIPS32_R_INST(0, reg,
0, 0, 0, MIPS32_OP_JR)
#define MIPS32_MFC0(gpr, cpr, sel) MIPS32_R_INST(MIPS32_OP_COP0,
MIPS32_COP0_MF, gpr, cpr, 0, sel)
+#define MIPS32_MOVE(dst, src) MIPS32_R_INST(17, 16, 0, src,
dst, 6)
#define MIPS32_MTC0(gpr, cpr, sel) MIPS32_R_INST(MIPS32_OP_COP0,
MIPS32_COP0_MT, gpr, cpr, 0, sel)
#define MIPS32_LBU(reg, off, base) MIPS32_I_INST(MIPS32_OP_LBU,
base, reg, off)
#define MIPS32_LHU(reg, off, base) MIPS32_I_INST(MIPS32_OP_LHU,
base, reg, off)
@@ -237,6 +280,8 @@ struct mips32_algorithm {
#define MIPS32_MFHI(reg) MIPS32_R_INST(0, 0, 0,
reg, 0, MIPS32_OP_MFHI)
#define MIPS32_MTLO(reg) MIPS32_R_INST(0, reg,
0, 0, 0, MIPS32_OP_MTLO)
#define MIPS32_MTHI(reg) MIPS32_R_INST(0, reg,
0, 0, 0, MIPS32_OP_MTHI)
+#define MIPS32_MUL(dst, src, t) MIPS32_R_INST(28, src,
t, dst, 0, MIPS32_OP_MUL)
+#define MIPS32_OR(dst, src, val) MIPS32_R_INST(0, src, val, dst,
0, 37)
#define MIPS32_ORI(tar, src, val) MIPS32_I_INST(MIPS32_OP_ORI,
src, tar, val)
#define MIPS32_XORI(tar, src, val) MIPS32_I_INST(MIPS32_OP_XORI,
src, tar, val)
#define MIPS32_RDHWR(tar, dst)
MIPS32_R_INST(MIPS32_OP_SPECIAL3, 0, tar, dst, 0, MIPS32_OP_RDHWR)
@@ -245,7 +290,8 @@ struct mips32_algorithm {
#define MIPS32_SW(reg, off, base) MIPS32_I_INST(MIPS32_OP_SW,
base, reg, off)
#define MIPS32_XOR(reg, val1, val2) MIPS32_R_INST(0, val1, val2,
reg, 0, MIPS32_OP_XOR)
#define MIPS32_SRL(reg, src, off) MIPS32_R_INST(0, 0, src, reg,
off, MIPS32_OP_SRL)
-#define MIPS32_SLTU(dst, src, tar)
MIPS32_R_INST(MIPS32_OP_SPECIAL, src, tar, dst, 0, MIPS32_OP_SLTU)
+#define MIPS32_SLTU(dst, tar, src)
MIPS32_R_INST(MIPS32_OP_SPECIAL, src, tar, dst, 0, MIPS32_OP_SLTU)
+#define MIPS32_SLLV(dst, tar, src)
MIPS32_R_INST(MIPS32_OP_SPECIAL, src, tar, dst, 0, MIPS32_OP_SLLV)
#define MIPS32_SYNCI(off, base)
MIPS32_I_INST(MIPS32_OP_REGIMM, base, MIPS32_OP_SYNCI, off)
#define MIPS32_SYNC 0xF
@@ -264,6 +310,8 @@ struct mips32_algorithm {
#define MIPS32_DRET 0x4200001F
#define MIPS32_SDBBP 0x7000003F /*
MIPS32_J_INST(MIPS32_OP_SPECIAL2, MIPS32_OP_SDBBP) */
#define MIPS16_SDBBP 0xE801
+#define MICRO_MIPS32_SDBBP 0x000046C0
+#define MICRO_MIPS_SDBBP 0x46C0
extern const struct command_registration mips32_command_handlers[];
@@ -299,6 +347,6 @@ int mips32_checksum_memory(struct target *target, uint32_t
address,
int mips32_blank_check_memory(struct target *target,
uint32_t address, uint32_t count, uint32_t *blank);
-int mips32_cp0_command (struct command_invocation *cmd);
-int mips32_scan_delay_command (struct command_invocation *cmd);
+int mips32_cp0_command(struct command_invocation *cmd);
+int mips32_scan_delay_command(struct command_invocation *cmd);
#endif /*MIPS32_H*/
diff --git a/src/target/mips32_pracc.c b/src/target/mips32_pracc.c
index e97626c..15f13c3 100644
--- a/src/target/mips32_pracc.c
+++ b/src/target/mips32_pracc.c
@@ -96,15 +96,17 @@ static int wait_for_pracc_rw(struct mips_ejtag *ejtag_info,
uint32_t *ctrl)
while (1) {
ejtag_ctrl = ejtag_info->ejtag_ctrl;
int retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
- if (retval != ERROR_OK)
+ if (retval != ERROR_OK) {
+ LOG_DEBUG("mips_ejtag_drscan_32 Failed");
return retval;
+ }
if (ejtag_ctrl & EJTAG_CTRL_PRACC)
break;
int timeout = timeval_ms() - then;
if (timeout > 1000) {
- LOG_DEBUG("DEBUGMODULE: No memory access in progress!");
+ LOG_DEBUG("Timeout: No memory access in progress!");
return ERROR_JTAG_DEVICE_ERROR;
}
}
@@ -117,8 +119,10 @@ static int wait_for_pracc_rw(struct mips_ejtag
*ejtag_info, uint32_t *ctrl)
static int mips32_pracc_read_ctrl_addr(struct mips_ejtag *ejtag_info)
{
int retval = wait_for_pracc_rw(ejtag_info, &ejtag_info->pa_ctrl);
- if (retval != ERROR_OK)
+ if (retval != ERROR_OK) {
+ LOG_DEBUG("wait_for_pracc_rw failed");
return retval;
+ }
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
ejtag_info->pa_addr = 0;
@@ -194,10 +198,13 @@ int mips32_pracc_exec(struct mips_ejtag *ejtag_info,
struct pracc_queue_info *ct
if (restart) {
if (restart_count < 3) {
/* max 3 restarts allowed */
retval =
mips32_pracc_clean_text_jump(ejtag_info);
- if (retval != ERROR_OK)
+ if (retval != ERROR_OK) {
+ LOG_DEBUG("mips32_pracc_clean_text_jump
failed");
return retval;
+ }
} else
return ERROR_JTAG_DEVICE_ERROR;
+
restart_count++;
restart = 0;
code_count = 0;
@@ -205,8 +212,10 @@ int mips32_pracc_exec(struct mips_ejtag *ejtag_info,
struct pracc_queue_info *ct
}
retval = mips32_pracc_read_ctrl_addr(ejtag_info);
/* update current pa info: control and address */
- if (retval != ERROR_OK)
+ if (retval != ERROR_OK) {
+ LOG_DEBUG("mips32_pracc_read_ctrl_addr failed");
return retval;
+ }
/* Check for read or write access */
if (ejtag_info->pa_ctrl & EJTAG_CTRL_PRNW) {
/* write/store access */
@@ -230,8 +239,10 @@ int mips32_pracc_exec(struct mips_ejtag *ejtag_info,
struct pracc_queue_info *ct
uint32_t data = 0;
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
retval = mips_ejtag_drscan_32(ejtag_info, &data);
- if (retval != ERROR_OK)
+ if (retval != ERROR_OK) {
+ LOG_DEBUG("mips_ejtag_drscan_32 failed");
return retval;
+ }
/* store data at param out, address based offset */
param_out[(ejtag_info->pa_addr -
MIPS32_PRACC_PARAM_OUT) / 4] = data;
@@ -283,7 +294,7 @@ int mips32_pracc_exec(struct mips_ejtag *ejtag_info, struct
pracc_queue_info *ct
}
} else {
if (ejtag_info->pa_addr !=
(MIPS32_PRACC_TEXT + code_count * 4)) {
- LOG_DEBUG("unexpected read
address in final check: %" PRIx32 ", expected: %x",
+ LOG_DEBUG("unexpected read
address in final check: %" PRIx32 ", expected: %" PRIx32,
ejtag_info->pa_addr,
MIPS32_PRACC_TEXT + code_count * 4);
return ERROR_JTAG_DEVICE_ERROR;
}
@@ -308,11 +319,15 @@ int mips32_pracc_exec(struct mips_ejtag *ejtag_info,
struct pracc_queue_info *ct
}
/* finish processor access, let the processor eat! */
retval = mips32_pracc_finish(ejtag_info);
- if (retval != ERROR_OK)
+ if (retval != ERROR_OK) {
+ LOG_DEBUG("mips32_pracc_finish failed");
return retval;
+ }
- if (instr == MIPS32_DRET) /* after leaving debug mode
nothing to do */
+ if (instr == MIPS32_DRET) { /* after leaving debug mode
nothing to do */
+ LOG_DEBUG("MIPS32_DRET executed");
return ERROR_OK;
+ }
if (store_pending == 0 && pass) { /* store access done,
but after passing pracc text */
LOG_DEBUG("warning: store access pass pracc text");
@@ -529,7 +544,7 @@ int mips32_pracc_read_mem(struct mips_ejtag *ejtag_info,
uint32_t addr, int size
pracc_add(&ctx, 0, MIPS32_MFC0(15, 31, 0));
/* restore $15 from DeSave */
if (size == 4) {
- ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx,
buf32);
+ ctx.retval = mips32_pracc_exec(ejtag_info, &ctx, buf32);
if (ctx.retval != ERROR_OK)
goto exit;
buf32 += this_round_count;
@@ -785,6 +800,7 @@ static int mips32_pracc_write_mem_generic(struct mips_ejtag
*ejtag_info,
pracc_add(&ctx, 0, MIPS32_LUI(8,
UPPER16(*buf32))); /* load upper and lower */
pracc_add(&ctx, 0, MIPS32_ORI(8, 8,
LOWER16(*buf32)));
}
+
pracc_add(&ctx, 0, MIPS32_SW(8, LOWER16(addr),
15)); /* store word to memory */
buf32++;
@@ -808,8 +824,11 @@ static int mips32_pracc_write_mem_generic(struct
mips_ejtag *ejtag_info,
pracc_add(&ctx, 0, MIPS32_MFC0(15, 31, 0));
/* restore $15 from DeSave */
ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL);
- if (ctx.retval != ERROR_OK)
+ if (ctx.retval != ERROR_OK) {
+ LOG_DEBUG("mips32_pracc_exec failed");
goto exit;
+ }
+
count -= this_round_count;
}
exit:
@@ -914,6 +933,7 @@ int mips32_pracc_write_regs(struct mips_ejtag *ejtag_info,
uint32_t *regs)
ejtag_info->reg8 = regs[8];
ejtag_info->reg9 = regs[9];
+ ejtag_info->reg10 = regs[10];
exit:
pracc_queue_free(&ctx);
return ctx.retval;
@@ -962,6 +982,7 @@ int mips32_pracc_read_regs(struct mips_ejtag *ejtag_info,
uint32_t *regs)
ejtag_info->reg8 = regs[8]; /* reg8 is saved but not restored, next
called function should restore it */
ejtag_info->reg9 = regs[9];
+ ejtag_info->reg10 = regs[10];
exit:
pracc_queue_free(&ctx);
return ctx.retval;
@@ -1016,8 +1037,10 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag
*ejtag_info, struct working_are
int retval, i;
uint32_t val, ejtag_ctrl, address;
- if (source->size < MIPS32_FASTDATA_HANDLER_SIZE)
+ if (source->size < MIPS32_FASTDATA_HANDLER_SIZE) {
+ LOG_DEBUG("source->size (%x) < MIPS32_FASTDATA_HANDLER_SIZE",
source->size);
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
if (write_t) {
handler_code[8] = MIPS32_LW(11, 0, 8); /* load data from probe
at fastdata area */
@@ -1030,6 +1053,7 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag
*ejtag_info, struct working_are
/* write program into RAM */
if (write_t != ejtag_info->fast_access_save) {
mips32_pracc_write_mem(ejtag_info, source->address, 4,
ARRAY_SIZE(handler_code), handler_code);
+
/* save previous operation to speed to any consecutive
read/writes */
ejtag_info->fast_access_save = write_t;
}
@@ -1041,8 +1065,10 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag
*ejtag_info, struct working_are
for (i = 0; i < (int) ARRAY_SIZE(jmp_code); i++) {
retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl);
- if (retval != ERROR_OK)
+ if (retval != ERROR_OK) {
+ LOG_DEBUG("wait_for_pracc_rw failed - retval = %d",
retval);
return retval;
+ }
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
mips_ejtag_drscan_32_out(ejtag_info, jmp_code[i]);
@@ -1055,18 +1081,24 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag
*ejtag_info, struct working_are
/* wait PrAcc pending bit for FASTDATA write */
retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl);
- if (retval != ERROR_OK)
+ if (retval != ERROR_OK) {
+ LOG_DEBUG("wait_for_pracc_rw failed - retval: %d", retval);
return retval;
+ }
/* next fetch to dmseg should be in FASTDATA_AREA, check */
address = 0;
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
retval = mips_ejtag_drscan_32(ejtag_info, &address);
- if (retval != ERROR_OK)
+ if (retval != ERROR_OK) {
+ LOG_DEBUG("mips_ejtag_drscan_32 failed - retval: %d", retval);
return retval;
+ }
- if (address != MIPS32_PRACC_FASTDATA_AREA)
+ if (address != MIPS32_PRACC_FASTDATA_AREA) {
+ LOG_DEBUG("address != MIPS32_PRACC_FASTDATA_AREA (0x%8.8x) -
0x%8.8x", MIPS32_PRACC_FASTDATA_AREA, address);
return ERROR_FAIL;
+ }
/* Send the load start address */
val = addr;
diff --git a/src/target/mips_common.c b/src/target/mips_common.c
index 03361a5..3fc5ba8 100644
--- a/src/target/mips_common.c
+++ b/src/target/mips_common.c
@@ -680,8 +680,23 @@ int mips_common_set_breakpoint(struct target *target,
if (ejtag_info->ejtag_version == EJTAG_VERSION_20)
comparator_list[bp_num].bp_value &= 0xFFFFFFFC;
- target_write_u32(target, comparator_list[bp_num].reg_address,
-
comparator_list[bp_num].bp_value);
+ if (mips32->mmips != MIPS32_ONLY) {
+ if ((breakpoint->length == 3) || (breakpoint->length ==
5)) {
+ comparator_list[bp_num].bp_value =
breakpoint->address | 1;
+
+ target_write_u32(target,
comparator_list[bp_num].reg_address,
+
comparator_list[bp_num].bp_value);
+ } else {
+ comparator_list[bp_num].bp_value =
breakpoint->address;
+ target_write_u32(target,
comparator_list[bp_num].reg_address,
+
comparator_list[bp_num].bp_value);
+ }
+ } else {
+ comparator_list[bp_num].bp_value = breakpoint->address;
+ target_write_u32(target,
comparator_list[bp_num].reg_address,
+
comparator_list[bp_num].bp_value);
+ }
+ comparator_list[bp_num].bp_value = breakpoint->address;
target_write_u32(target, comparator_list[bp_num].reg_address +
ejtag_info->ejtag_ibm_offs, 0x00000000);
@@ -695,17 +710,28 @@ int mips_common_set_breakpoint(struct target *target,
} else if (breakpoint->type == BKPT_SOFT) {
LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
- if (breakpoint->length == 4) {
+ /* IF GDB sends bp->length 5 for microMips support then change
it to 4 */
+ /* Check if kind field, is indicated microMips Break */
+ /* Verify address is aligned 4 byte boundary and replacing a
32-bit instruction */
+ if ((breakpoint->length == 4) || ((breakpoint->length == 5) &&
+
((breakpoint->address % 4) == 0))) {
uint32_t verify = 0xffffffff;
+ uint32_t breakpt_instr;
- retval = target_read_memory(target,
breakpoint->address, breakpoint->length, 1,
-
breakpoint->orig_instr);
+ /* Remove isa_mode info from length to adjust to
correct instruction size */
+ if (breakpoint->length == 5)
+ breakpt_instr = MICRO_MIPS32_SDBBP;
+ else
+ breakpt_instr = MIPS32_SDBBP;
+
+ retval = target_read_memory(target,
breakpoint->address, (breakpoint->length & 0xE),
+
1, breakpoint->orig_instr);
if (retval != ERROR_OK) {
LOG_DEBUG("target_read_memory failed");
return retval;
}
- retval = target_write_u32(target, breakpoint->address,
MIPS32_SDBBP);
+ retval = target_write_u32(target, breakpoint->address,
breakpt_instr);
if (retval != ERROR_OK) {
LOG_DEBUG("target_write_u32 failed");
return retval;
@@ -717,13 +743,28 @@ int mips_common_set_breakpoint(struct target *target,
return retval;
}
- if (verify != MIPS32_SDBBP) {
+ if ((breakpt_instr == MIPS32_SDBBP) && (verify !=
MIPS32_SDBBP)) {
LOG_ERROR("Unable to set 32bit breakpoint at
address %08" PRIx32
" - check that memory is
read/writable", breakpoint->address);
return ERROR_OK;
+ } else {
+ if ((breakpt_instr == MICRO_MIPS32_SDBBP) &&
(verify != MICRO_MIPS32_SDBBP)) {
+ LOG_ERROR("Unable to set
microMips32 breakpoint at address %08" PRIx32
+ " - check
that memory is read/writable", breakpoint->address);
+ return ERROR_OK;
+ }
}
} else {
uint16_t verify = 0xffff;
+ uint16_t breakpt_instr;
+
+ if ((breakpoint->length == 3) || ((breakpoint->length
== 5) &&
+
((breakpoint->address % 4) != 0))) {
+ breakpoint->length = 2;
+ breakpt_instr = MICRO_MIPS_SDBBP;
+ } else {
+ breakpt_instr = MIPS16_SDBBP;
+ }
retval = target_read_memory(target,
breakpoint->address, breakpoint->length, 1,
breakpoint->orig_instr);
@@ -732,7 +773,7 @@ int mips_common_set_breakpoint(struct target *target,
return retval;
}
- retval = target_write_u16(target, breakpoint->address,
MIPS16_SDBBP);
+ retval = target_write_u16(target, breakpoint->address,
breakpt_instr);
if (retval != ERROR_OK) {
LOG_DEBUG("target_write_u16 failed");
return retval;
@@ -744,10 +785,16 @@ int mips_common_set_breakpoint(struct target *target,
return retval;
}
- if (verify != MIPS16_SDBBP) {
+ if ((breakpt_instr == MIPS16_SDBBP) && (verify !=
MIPS16_SDBBP)) {
LOG_ERROR("Unable to set 16bit breakpoint at
address %08" PRIx32
" - check that memory is
read/writable", breakpoint->address);
return ERROR_OK;
+ } else {
+ if ((breakpt_instr == MICRO_MIPS_SDBBP) &&
(verify != MICRO_MIPS_SDBBP)) {
+ LOG_ERROR("Unable to set
microMips breakpoint at address %08" PRIx32
+ " - check
that memory is read/writable", breakpoint->address);
+ return ERROR_OK;
+ }
}
}
@@ -790,7 +837,7 @@ int mips_common_unset_breakpoint(struct target *target,
} else {
/* restore original instruction (kept in target endianness) */
LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
- if (breakpoint->length == 4) {
+ if ((breakpoint->length == 4) || ((breakpoint->length == 5) &&
((breakpoint->address % 4) == 0))) {
uint32_t current_instr;
/* check that user program has not modified breakpoint
instruction */
@@ -809,7 +856,7 @@ int mips_common_unset_breakpoint(struct target *target,
*/
current_instr = target_buffer_get_u32(target, (uint8_t
*)¤t_instr);
- if (current_instr == MIPS32_SDBBP) {
+ if ((current_instr == MIPS32_SDBBP) || (current_instr
== MICRO_MIPS32_SDBBP)) {
retval = target_write_memory(target,
breakpoint->address, 4, 1, breakpoint->orig_instr);
if (retval != ERROR_OK)
return retval;
@@ -829,7 +876,7 @@ int mips_common_unset_breakpoint(struct target *target,
}
current_instr = target_buffer_get_u16(target, (uint8_t
*)¤t_instr);
- if (current_instr == MIPS16_SDBBP) {
+ if ((current_instr == MIPS16_SDBBP) || (current_instr
== MICRO_MIPS_SDBBP)) {
retval = target_write_memory(target,
breakpoint->address, 2, 1, breakpoint->orig_instr);
if (retval != ERROR_OK) {
LOG_DEBUG("target_write_memory failed");
@@ -1074,7 +1121,6 @@ int mips_common_write_memory(struct target *target,
uint32_t address,
int retval = mips_common_bulk_write_memory(target, address,
count, buffer);
if (retval == ERROR_OK)
return ERROR_OK;
-
LOG_WARNING("Falling back to non-bulk write");
}
diff --git a/src/target/mips_mAptiv.c b/src/target/mips_mAptiv.c
new file mode 100644
index 0000000..e4cbe65
--- /dev/null
+++ b/src/target/mips_mAptiv.c
@@ -0,0 +1,114 @@
+/***************************************************************************
+ * Copyright (C) 2008 by Spencer Oliver *
+ * s...@spen-soft.co.uk *
+ * *
+ * Copyright (C) 2008 by David T.L. Wong *
+ * *
+ * Copyright (C) 2009 by David N. Claffey <dnclaf...@gmail.com> *
+ * *
+ * Copyright (C) 2011 by Drasko DRASKOVIC *
+ * drasko.drasko...@gmail.com *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ ***************************************************************************/
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "breakpoints.h"
+#include "mips32.h"
+#include "mips_m4k.h"
+#include "mips_mAptiv.h"
+#include "mips_common.h"
+#include "mips32_dmaacc.h"
+#include "target_type.h"
+#include "register.h"
+
+static int mips_mAptiv_init_target(struct command_context *cmd_ctx,
+ struct target *target)
+{
+ mips32_build_reg_cache(target);
+
+ return ERROR_OK;
+}
+
+static int mips_mAptiv_init_arch_info(struct target *target,
+ struct mips_mAptiv_common *mips_mAptiv, struct jtag_tap *tap)
+{
+ struct mips32_common *mips32 = &mips_mAptiv->mips32;
+
+ mips_mAptiv->common_magic = MIPSMAPTIV_COMMON_MAGIC;
+
+ /* initialize mips4k specific info */
+ mips32_init_arch_info(target, mips32, tap);
+ mips32->arch_info = mips_mAptiv;
+
+ return ERROR_OK;
+}
+
+static int mips_mAptiv_target_create(struct target *target, Jim_Interp *interp)
+{
+ struct mips_mAptiv_common *mips_mAptiv = calloc(1, sizeof(struct
mips_mAptiv_common));
+
+ mips_mAptiv_init_arch_info(target, mips_mAptiv, target->tap);
+
+ return ERROR_OK;
+}
+
+static const struct command_registration mips_mAptiv_exec_command_handlers[] =
{
+ COMMAND_REGISTRATION_DONE
+};
+
+const struct command_registration mips_mAptiv_command_handlers[] = {
+ {
+ .chain = mips32_command_handlers,
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+struct target_type mips_mAptiv_target = {
+ .name = "mips_mAptiv",
+
+ .poll = mips_common_poll,
+ .arch_state = mips32_arch_state,
+
+ .halt = mips_common_halt,
+ .resume = mips_common_resume,
+ .step = mips_common_step,
+
+ .assert_reset = mips_common_assert_reset,
+ .deassert_reset = mips_common_deassert_reset,
+
+ .get_gdb_reg_list = mips32_get_gdb_reg_list,
+
+ .read_memory = mips_common_read_memory,
+ .write_memory = mips_common_write_memory,
+ .checksum_memory = mips32_checksum_memory,
+ .blank_check_memory = mips32_blank_check_memory,
+
+ .run_algorithm = mips32_run_algorithm,
+
+ .add_breakpoint = mips_common_add_breakpoint,
+ .remove_breakpoint = mips_common_remove_breakpoint,
+ .add_watchpoint = mips_common_add_watchpoint,
+ .remove_watchpoint = mips_common_remove_watchpoint,
+
+ .commands = mips_mAptiv_command_handlers,
+ .target_create = mips_mAptiv_target_create,
+ .init_target = mips_common_init_target,
+ .examine = mips_common_examine,
+};
diff --git a/src/target/mips_mAptiv.h b/src/target/mips_mAptiv.h
new file mode 100644
index 0000000..2ae6cbb
--- /dev/null
+++ b/src/target/mips_mAptiv.h
@@ -0,0 +1,47 @@
+/***************************************************************************
+ * Copyright (C) 2008 by Spencer Oliver *
+ * s...@spen-soft.co.uk *
+ * *
+ * Copyright (C) 2008 by David T.L. Wong *
+ * *
+ * Copyright (C) 2011 by Drasko DRASKOVIC *
+ * drasko.drasko...@gmail.com *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ ***************************************************************************/
+
+#ifndef MIPS_MAPTIV_H
+#define MIPS_MAPTIV_H
+
+struct target;
+
+#define MIPSMAPTIV_COMMON_MAGIC 0xB321B321
+
+struct mips_mAptiv_common {
+ uint32_t common_magic;
+ bool is_pic32mx;
+ struct mips32_common mips32;
+};
+
+inline struct mips_mAptiv_common *target_to_mAptiv(struct target *target)
+{
+ return container_of(target->arch_info,
+ struct mips_mAptiv_common, mips32);
+}
+
+extern const struct command_registration mips_mAptiv_command_handlers[];
+
+#endif /*MIPS_MAPTIV_H*/
--
------------------------------------------------------------------------------
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