This is an automated email from Gerrit.
Paul Fertser (fercer...@gmail.com) just uploaded a new patch set to Gerrit,
which you can find at http://openocd.zylin.com/2769
-- gerrit
commit 99afd135b4ca475a7e7ff7e3511a649ba9815c0f
Author: Paul Fertser <fercer...@gmail.com>
Date: Fri May 15 13:16:12 2015 +0300
manual: fix all overfull and underfull hboxes
Change-Id: Id84f16de5a3d1907e196d13007a312593bb6670a
Signed-off-by: Paul Fertser <fercer...@gmail.com>
diff --git a/doc/openocd.texi b/doc/openocd.texi
index ce0bf13..0e197c3 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -471,7 +471,7 @@ SWD and not JTAG, thus not supported.
@itemize @bullet
@item @b{Raisonance RLink}
-@* Link:
@url{http://www.mcu-raisonance.com/~rlink-debugger-programmer__microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html}
+@* Link:
@url{http://www.mcu-raisonance.com/~rlink-debugger-programmer__@/microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html}
@item @b{STM32 Primer}
@* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
@item @b{STM32 Primer2}
@@ -4014,14 +4014,14 @@ not a CPU type. It is based on the ARMv5 architecture.
@item @code{openrisc} -- this is an OpenRISC 1000 core.
The current implementation supports three JTAG TAP cores:
@itemize @minus
-@item @code{OpenCores TAP} (See: @emph{http://opencores.org/project,jtag})
-@item @code{Altera Virtual JTAG TAP} (See:
@emph{http://www.altera.com/literature/ug/ug_virtualjtag.pdf})
-@item @code{Xilinx BSCAN_* virtual JTAG interface} (See:
@emph{http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/spartan6_hdl.pdf})
+@item @code{OpenCores TAP} (See: @url{http://opencores.org/project,jtag})
+@item @code{Altera Virtual JTAG TAP} (See:
@url{http://www.altera.com/literature/ug/ug_virtualjtag.pdf})
+@item @code{Xilinx BSCAN_* virtual JTAG interface} (See:
@url{http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/spartan6_hdl.pdf})
@end itemize
And two debug interfaces cores:
@itemize @minus
-@item @code{Advanced debug interface} (See:
@emph{http://opencores.org/project,adv_debug_sys})
-@item @code{SoC Debug Interface} (See:
@emph{http://opencores.org/project,dbg_interface})
+@item @code{Advanced debug interface} (See:
@url{http://opencores.org/project,adv_debug_sys})
+@item @code{SoC Debug Interface} (See:
@url{http://opencores.org/project,dbg_interface})
@end itemize
@end itemize
@end deffn
@@ -4345,7 +4345,8 @@ proc my_attach_proc @{ @} @{
mychip.cpu configure -event gdb-attach my_attach_proc
mychip.cpu configure -event gdb-attach @{
echo "Reset..."
- # To make flash probe and gdb load to flash work we need a reset init.
+ # To make flash probe and gdb load to flash work
+ # we need a reset init.
reset init
@}
@end example
@@ -5430,7 +5431,8 @@ The @var{str7x} driver defines one mandatory parameter,
@var{variant},
which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
@example
-flash bank $_FLASHNAME str7x 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
+flash bank $_FLASHNAME str7x \
+ 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
@end example
@deffn Command {str7x disable_jtag} bank
@@ -5676,7 +5678,8 @@ based controllers. A known limitation is that the Info
memory can't be
read or verified as it's not memory mapped.
@example
-flash bank <name> mdr <base> <size> 0 0 <target#> @var{type} @var{page_count}
@var{sec_count}
+flash bank <name> mdr <base> <size> \
+ 0 0 <target#> @var{type} @var{page_count} @var{sec_count}
@end example
@itemize @bullet
@@ -5688,9 +5691,11 @@ flash bank <name> mdr <base> <size> 0 0 <target#>
@var{type} @var{page_count} @v
Example usage:
@example
if @{ [info exists IMEMORY] && [string equal $IMEMORY true] @} @{
- flash bank $@{_CHIPNAME@}_info.flash mdr 0x00000000 0x01000 0 0
$_TARGETNAME 1 1 4
+ flash bank $@{_CHIPNAME@}_info.flash mdr 0x00000000 0x01000 \
+ 0 0 $_TARGETNAME 1 1 4
@} else @{
- flash bank $_CHIPNAME.flash mdr 0x00000000 0x20000 0 0 $_TARGETNAME 0 32 4
+ flash bank $_CHIPNAME.flash mdr 0x00000000 0x20000 \
+ 0 0 $_TARGETNAME 0 32 4
@}
@end example
@end deffn
@@ -6638,7 +6643,8 @@ In addition the following arguments may be specifed:
proc load_image_bin @{fname foffset address length @} @{
# Load data from fname filename at foffset offset to
# target at address. Load at most length bytes.
- load_image $fname [expr $address - $foffset] bin $address $length
+ load_image $fname [expr $address - $foffset] bin \
+ $address $length
@}
@end example
@end deffn
@@ -7563,9 +7569,13 @@ $ stty -F /dev/ttyUSB1 38400
(FT2232H's base frequency is 60MHz, spd_cust allows to alias 38400
baud with our custom divisor to get 12MHz)
@item @code{itmdump -f /dev/ttyUSB1 -d1}
-@item @code{openocd -f interface/stlink-v2-1.cfg -c "transport select
-hla_swd" -f target/stm32l1.cfg -c "tpiu config external uart off
-24000000 12000000"}
+@item OpenOCD invocation line:
+@example
+openocd -f interface/stlink-v2-1.cfg \
+ -c "transport select hla_swd" \
+ -f target/stm32l1.cfg \
+ -c "tpiu config external uart off 24000000 12000000"
+@end example
@end enumerate
@end deffn
@@ -8442,9 +8452,11 @@ Cyg_Thread::thread_list,
Cyg_Scheduler_Base::current_thread.
@item ThreadX symbols
_tx_thread_current_ptr, _tx_thread_created_ptr, _tx_thread_created_count.
@item FreeRTOS symbols
+@raggedright
pxCurrentTCB, pxReadyTasksLists, xDelayedTaskList1, xDelayedTaskList2,
pxDelayedTaskList, pxOverflowDelayedTaskList, xPendingReadyList,
uxCurrentNumberOfTasks, uxTopUsedPriority.
+@end raggedright
@item linux symbols
init_task.
@item ChibiOS symbols
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