This is an automated email from Gerrit.
Ladislav B?bel (ladaba...@seznam.cz) just uploaded a new patch set to Gerrit,
which you can find at http://openocd.zylin.com/2010
-- gerrit
commit a6858e58c7b86d343195d78a874ae51b37f2d2ec
Author: Ladislav Bábel <ladaba...@seznam.cz>
Date: Sun Mar 2 21:35:30 2014 +0100
Add new flash driver for Silicon Laboratories SiM3 microcontroller family
New driver
New script only for stlik for now
Driver added to the documentation
Change-Id: Ifa5374805015c3d75d82646b664449e0eb37f6ac
Signed-off-by: Ladislav Bábel <ladaba...@seznam.cz>
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 814a239..35840d3 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -1446,49 +1446,49 @@ When a chip has multiple TAPs (maybe it has both ARM
and DSP cores),
the target config file defines all of them.
@example
$ ls target
-aduc702x.cfg lpc1763.cfg
-am335x.cfg lpc1764.cfg
-amdm37x.cfg lpc1765.cfg
-ar71xx.cfg lpc1766.cfg
-at32ap7000.cfg lpc1767.cfg
-at91r40008.cfg lpc1768.cfg
-at91rm9200.cfg lpc1769.cfg
-at91sam3ax_4x.cfg lpc1788.cfg
-at91sam3ax_8x.cfg lpc17xx.cfg
-at91sam3ax_xx.cfg lpc1850.cfg
-at91sam3nXX.cfg lpc2103.cfg
-at91sam3sXX.cfg lpc2124.cfg
-at91sam3u1c.cfg lpc2129.cfg
-at91sam3u1e.cfg lpc2148.cfg
-at91sam3u2c.cfg lpc2294.cfg
-at91sam3u2e.cfg lpc2378.cfg
-at91sam3u4c.cfg lpc2460.cfg
-at91sam3u4e.cfg lpc2478.cfg
-at91sam3uxx.cfg lpc2900.cfg
-at91sam3XXX.cfg lpc2xxx.cfg
-at91sam4sd32x.cfg lpc3131.cfg
-at91sam4sXX.cfg lpc3250.cfg
-at91sam4XXX.cfg lpc4350.cfg
-at91sam7se512.cfg lpc4350.cfg.orig
-at91sam7sx.cfg mc13224v.cfg
-at91sam7x256.cfg nuc910.cfg
-at91sam7x512.cfg omap2420.cfg
-at91sam9260.cfg omap3530.cfg
-at91sam9260_ext_RAM_ext_flash.cfg omap4430.cfg
-at91sam9261.cfg omap4460.cfg
-at91sam9263.cfg omap5912.cfg
-at91sam9.cfg omapl138.cfg
-at91sam9g10.cfg pic32mx.cfg
-at91sam9g20.cfg pxa255.cfg
-at91sam9g45.cfg pxa270.cfg
-at91sam9rl.cfg pxa3xx.cfg
-atmega128.cfg readme.txt
-avr32.cfg samsung_s3c2410.cfg
-c100.cfg samsung_s3c2440.cfg
-c100config.tcl samsung_s3c2450.cfg
-c100helper.tcl samsung_s3c4510.cfg
-c100regs.tcl samsung_s3c6410.cfg
-cs351x.cfg sharp_lh79532.cfg
+aduc702x.cfg lpc1764.cfg
+am335x.cfg lpc1765.cfg
+amdm37x.cfg lpc1766.cfg
+ar71xx.cfg lpc1767.cfg
+at32ap7000.cfg lpc1768.cfg
+at91r40008.cfg lpc1769.cfg
+at91rm9200.cfg lpc1788.cfg
+at91sam3ax_4x.cfg lpc17xx.cfg
+at91sam3ax_8x.cfg lpc1850.cfg
+at91sam3ax_xx.cfg lpc2103.cfg
+at91sam3nXX.cfg lpc2124.cfg
+at91sam3sXX.cfg lpc2129.cfg
+at91sam3u1c.cfg lpc2148.cfg
+at91sam3u1e.cfg lpc2294.cfg
+at91sam3u2c.cfg lpc2378.cfg
+at91sam3u2e.cfg lpc2460.cfg
+at91sam3u4c.cfg lpc2478.cfg
+at91sam3u4e.cfg lpc2900.cfg
+at91sam3uxx.cfg lpc2xxx.cfg
+at91sam3XXX.cfg lpc3131.cfg
+at91sam4sd32x.cfg lpc3250.cfg
+at91sam4sXX.cfg lpc4350.cfg
+at91sam4XXX.cfg lpc4350.cfg.orig
+at91sam7se512.cfg mc13224v.cfg
+at91sam7sx.cfg nuc910.cfg
+at91sam7x256.cfg omap2420.cfg
+at91sam7x512.cfg omap3530.cfg
+at91sam9260.cfg omap4430.cfg
+at91sam9260_ext_RAM_ext_flash.cfg omap4460.cfg
+at91sam9261.cfg omap5912.cfg
+at91sam9263.cfg omapl138.cfg
+at91sam9.cfg pic32mx.cfg
+at91sam9g10.cfg pxa255.cfg
+at91sam9g20.cfg pxa270.cfg
+at91sam9g45.cfg pxa3xx.cfg
+at91sam9rl.cfg readme.txt
+atmega128.cfg samsung_s3c2410.cfg
+avr32.cfg samsung_s3c2440.cfg
+c100.cfg samsung_s3c2450.cfg
+c100config.tcl samsung_s3c4510.cfg
+c100helper.tcl samsung_s3c6410.cfg
+c100regs.tcl sharp_lh79532.cfg
+cs351x.cfg sim3x_stlink.cfg
davinci.cfg smp8634.cfg
dragonite.cfg spear3xx.cfg
dsp56321.cfg stellaris.cfg
@@ -1523,6 +1523,7 @@ lpc1754.cfg ti_dm6446.cfg
lpc1756.cfg tmpa900.cfg
lpc1758.cfg tmpa910.cfg
lpc1759.cfg u8500.cfg
+lpc1763.cfg
@end example
@item @emph{more} ... browse for other library files which may be useful.
For example, there are various generic and CPU-specific utilities.
@@ -5591,6 +5592,18 @@ flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
@end example
@end deffn
+@deffn {Flash Driver} sim3x
+All members of the SiM3 microcontroller family from Silicon Laboratories
+include internal flash and use ARM Cortex M3 cores.
+The @var{fm3} driver uses the @var{size} parameter to select the
+correct size of flash bank. If @var{size} is set to 0, default flash bank size
+256kB will be used.
+
+@example
+flash bank $_FLASHNAME sim3x 0 $_CPUROMSIZE 0 0 $_TARGETNAME
+@end example
+@end deffn
+
@subsection str9xpec driver
@cindex str9xpec
diff --git a/src/flash/nor/Makefile.am b/src/flash/nor/Makefile.am
index 3168147..4940430 100644
--- a/src/flash/nor/Makefile.am
+++ b/src/flash/nor/Makefile.am
@@ -43,7 +43,8 @@ NOR_DRIVERS = \
kinetis.c \
mini51.c \
nuc1x.c \
- nrf51.c
+ nrf51.c \
+ sim3x.c
noinst_HEADERS = \
core.h \
diff --git a/src/flash/nor/drivers.c b/src/flash/nor/drivers.c
index ed631a3..817ea5b 100644
--- a/src/flash/nor/drivers.c
+++ b/src/flash/nor/drivers.c
@@ -56,6 +56,7 @@ extern struct flash_driver mdr_flash;
extern struct flash_driver mini51_flash;
extern struct flash_driver nuc1x_flash;
extern struct flash_driver nrf51_flash;
+extern struct flash_driver sim3x_flash;
/**
* The list of built-in flash drivers.
@@ -96,6 +97,7 @@ static struct flash_driver *flash_drivers[] = {
&mini51_flash,
&nuc1x_flash,
&nrf51_flash,
+ &sim3x_flash,
NULL,
};
diff --git a/src/flash/nor/sim3x.c b/src/flash/nor/sim3x.c
new file mode 100755
index 0000000..e8d065d
--- /dev/null
+++ b/src/flash/nor/sim3x.c
@@ -0,0 +1,833 @@
+/***************************************************************************
+ * Copyright (C) 2014 by Ladislav B�bel *
+ * ladaba...@seznam.cz *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ ***************************************************************************/
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "imp.h"
+#include <helper/binarybuffer.h>
+#include <helper/time_support.h>
+#include <target/algorithm.h>
+#include <target/cortex_m.h>
+
+#define DEVICEID0_DEVICEID0 (0x400490C0)
+#define DEVICEID0_DEVICEID1 (0x400490D0)
+#define DEVICEID0_DEVICEID2 (0x400490E0)
+#define DEVICEID0_DEVICEID3 (0x400490F0)
+
+#define LOCK_WORD (0x0003FFFC)
+
+#define FLASH_BASE_ADDRESS (0x00000000)
+
+// SI32_RSTSRC_0
+#define RSTSRC0_RESETEN ( (sim3x_register_all_set_clr *)0x4002D060 )
+#define RSTSRC0_RESETEN_VMONREN_MASK (0x00000004)
+
+// SI32_VMON_0
+#define VMON0_CONTROL ( (sim3x_register_all_set_clr *)0x4002F000 )
+#define VMON0_CONTROL_VMONEN_MASK (0x80000000)
+
+// SI32_CLKCTRL_0
+#define CLKCTRL0_APBCLKG0 ( (sim3x_register_all_set_clr *)0x4002D020 )
+#define CLKCTRL0_APBCLKG0_FLCTRLCEN_MASK (0x40000000)
+
+// SI32_FLASHCTRL_0
+#define FLASHCTRL0_CONFIG ( (sim3x_register_all_set_clr *)0x4002E000 )
+#define FLASHCTRL0_CONFIG_ERASEEN_MASK (0x00040000)
+#define FLASHCTRL0_CONFIG_BUSYF_MASK (0x00100000)
+
+#define FLASHCTRL0_WRADDR (0x4002E0A0)
+#define FLASHCTRL0_WRDATA (0x4002E0B0)
+
+#define FLASHCTRL0_KEY (0x4002E0C0)
+#define FLASHCTRL0_KEY_INITIAL_UNLOCK (0x000000A5)
+#define FLASHCTRL0_KEY_SINGLE_UNLOCK (0x000000F1)
+#define FLASHCTRL0_KEY_MULTIPLE_UNLOCK (0x000000F2)
+#define FLASHCTRL0_KEY_MULTIPLE_LOCK (0x0000005A)
+
+#define FLASH_BUSY_TIMEOUT (100)
+
+// SI32_WDTIMER_0
+#define WDTIMER0_CONTROL ( (sim3x_register_all_set_clr *)0x40030000 )
+#define WDTIMER0_CONTROL_DBGMD_MASK (0x00000002)
+
+#define WDTIMER0_STATUS ( (sim3x_register_all_set_clr *)0x40030010 )
+#define WDTIMER0_STATUS_KEYSTS_MASK (0x00000001)
+#define WDTIMER0_STATUS_PRIVSTS_MASK (0x00000002)
+
+#define WDTIMER0_THRESHOLD (0x40030020)
+
+#define WDTIMER0_WDTKEY (0x40030030)
+#define WDTIMER0_KEY_ATTN (0x000000A5)
+#define WDTIMER0_KEY_WRITE (0x000000F1)
+#define WDTIMER0_KEY_RESET (0x000000CC)
+#define WDTIMER0_KEY_DISABLE (0x000000DD)
+#define WDTIMER0_KEY_START (0x000000EE)
+#define WDTIMER0_KEY_LOCK (0x000000FF)
+
+// RSTSRC0
+#define RSTSRC0_RESETEN ( (sim3x_register_all_set_clr *)0x4002D060 )
+#define RSTSRC0_RESETEN_SWREN_MASK (0x00000040)
+
+typedef struct
+{
+ uint32_t all;
+ uint32_t set;
+ uint32_t clr;
+} sim3x_register_all_set_clr;
+
+typedef union
+{
+ uint32_t u32;
+ int32_t i32;
+ uint16_t u16[2];
+ int16_t i16[2];
+ uint8_t u8[4];
+ int8_t i8[4];
+} Uu32;
+
+typedef struct
+{
+ int probed;
+ int flash_locked; // 1 => Locked, 0 => Unlocked by
0xFFFFFFFF, -1 => Unlocked by 0x00000000 (erase needed for lock)
+ uint16_t flash_size_KB;
+ uint16_t flash_page_size;
+ uint16_t ram_size_KB;
+ uint16_t part_number;
+ char part_family;
+ uint8_t device_revision;
+ char device_package[4];
+} Sim3x_info;
+
+static int sim3x_flash_lock_check(struct flash_bank *bank)
+{
+ int ret;
+ uint32_t lockWord;
+
+ ret = target_read_u32(bank->target, LOCK_WORD, &lockWord);
+ if(ERROR_OK != ret)
+ {
+ LOG_ERROR("Can not read Lock Word");
+ return ret;
+ }
+
+ switch(lockWord)
+ {
+ case 0x00000000:
+ lockWord = -1; // Unlocked (erase needed for lock)
+ break;
+
+ case 0xFFFFFFFF:
+ lockWord = 0; // Unlocked
+ break;
+
+ default:
+ lockWord = 1; // Locked
+ break;
+ }
+
+ ( (Sim3x_info *)bank->driver_priv )->flash_locked = lockWord;
+
+ return ERROR_OK;
+}
+
+static int sim3x_read_info(struct flash_bank *bank)
+{
+ int ret;
+ //int i;
+ uint32_t cpuid = 0;
+ //Uu32 uDeviceId;
+ //char part_num_string[4];
+ Sim3x_info * sim3x_info; // 3 M
+ //const uint8_t DEVICEID2[4] = {0x33, 0x4D, 0x00, 0x00};
+
+ sim3x_info = bank->driver_priv;
+
+ // Core check
+ ret = target_read_u32(bank->target, CPUID, &cpuid);
+ if(ERROR_OK != ret)
+ return ret;
+
+ if( ( (cpuid >> 4) & 0xfff ) != 0xc23 )
+ {
+ LOG_ERROR("Target is not CortexM3");
+ return ERROR_FAIL;
+ }
+
+ // ---------!Reading of DEVICEID is not working correct!-----------
+
+/*
+ // MCU check
+ ret = target_read_u32(bank->target, DEVICEID0_DEVICEID2,
&uDeviceId.u32);
+ if(ERROR_OK != ret)
+ return ret;
+
+ for(i = 0; i < 4; i++)
+ {
+ if(uDeviceId.u8[i] != DEVICEID2[i])
+ {
+ LOG_ERROR("Unsupported MCU");
+ return ERROR_FAIL;
+ }
+ }
+
+ // Family and Part number
+ ret = target_read_u32(bank->target, DEVICEID0_DEVICEID1,
&uDeviceId.u32);
+ if(ERROR_OK != ret)
+ return ret;
+
+ part_num_string[0] = uDeviceId.i8[2];
+ part_num_string[1] = uDeviceId.i8[1];
+ part_num_string[2] = uDeviceId.i8[0];
+ part_num_string[3] = 0;
+
+ i = atoi(part_num_string);
+
+ if( !isalpha(uDeviceId.i8[3]) || i < 100 || i > 999 )
+ {
+ LOG_ERROR("Unsupported MCU");
+ return ERROR_FAIL;
+ }
+
+ sim3x_info->part_family = uDeviceId.i8[3];
+ sim3x_info->part_number = i;
+
+ // Package and Revision
+ ret = target_read_u32(bank->target, DEVICEID0_DEVICEID0,
&uDeviceId.u32);
+ if(ERROR_OK != ret)
+ return ret;
+
+ sim3x_info->device_package[0] = uDeviceId.i8[3];
+ sim3x_info->device_package[1] = uDeviceId.i8[2];
+ sim3x_info->device_package[2] = uDeviceId.i8[1];
+ sim3x_info->device_package[3] = 0;
+
+ sim3x_info->device_revision = uDeviceId.u8[0];
+*/
+ sim3x_info->part_family = 'C';
+ sim3x_info->part_number = 167;
+ sim3x_info->device_package[0] = 'B';
+ sim3x_info->device_package[1] = 'G';
+ sim3x_info->device_package[2] = 'Q';
+ sim3x_info->device_package[3] = 0;
+ sim3x_info->device_revision = 1;
+
+ // Flash lock
+ ret = sim3x_flash_lock_check(bank);
+ if(ERROR_OK != ret)
+ return ret;
+
+ // TO DO: auto select sizes
+ sim3x_info->ram_size_KB = 32;
+ sim3x_info->flash_size_KB = bank->size == 0 ? 256 : bank->size / 1024;
+ sim3x_info->flash_page_size = 1024;
+
+ return ERROR_OK;
+}
+
+/* flash bank sim3x 0 0 0 0 <target#> */
+FLASH_BANK_COMMAND_HANDLER(sim3x_flash_bank_command)
+{
+ Sim3x_info * sim3x_info;
+
+ if (CMD_ARGC < 6)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ sim3x_info = malloc( sizeof(Sim3x_info) );
+ sim3x_info->probed = 0;
+ bank->driver_priv = sim3x_info;
+
+ return ERROR_OK;
+}
+
+static int sim3x_erase_page(struct flash_bank *bank, uint32_t addr)
+{
+ int ret, i;
+ uint32_t temp;
+ struct target * target;
+
+ target = bank->target;
+
+ i = FLASH_BUSY_TIMEOUT;
+ do
+ {
+ ret = target_read_u32(target,
(uint32_t)&FLASHCTRL0_CONFIG->all, &temp);
+ if(ERROR_OK != ret)
+ return ret;
+
+ if( (temp & FLASHCTRL0_CONFIG_BUSYF_MASK) == 0 )
+ { // If is not busy
+ if( (temp & FLASHCTRL0_CONFIG_ERASEEN_MASK) == 0 )
+ { // If erase is not enabled
+ // Enter Flash Erase Mode
+ ret = target_write_u32(target,
(uint32_t)&FLASHCTRL0_CONFIG->set, FLASHCTRL0_CONFIG_ERASEEN_MASK);
+ if(ERROR_OK != ret)
+ return ret;
+ }
+
+ // Write the address of the Flash page to WRADDR
+ ret = target_write_u32(target, FLASHCTRL0_WRADDR, addr);
+ if(ERROR_OK != ret)
+ return ret;
+
+ // Write the inital unlock value to KEY
+ ret = target_write_u32(target, FLASHCTRL0_KEY,
FLASHCTRL0_KEY_INITIAL_UNLOCK);
+ if(ERROR_OK != ret)
+ return ret;
+
+ // Write the single unlock value to KEY
+ ret = target_write_u32(target, FLASHCTRL0_KEY,
FLASHCTRL0_KEY_SINGLE_UNLOCK);
+ if(ERROR_OK != ret)
+ return ret;
+
+ // Write any value to WRDATA to initiate the page erase
+ ret = target_write_u32(target, FLASHCTRL0_WRDATA, 0);
+ if(ERROR_OK != ret)
+ return ret;
+
+ return ERROR_OK;
+ }
+
+ alive_sleep(1);
+ }
+ while(--i);
+
+ LOG_ERROR("timed out waiting for FLASHCTRL0_CONFIG_BUSYF");
+ return ERROR_FAIL;
+}
+
+static int sim3x_flash_erase(struct flash_bank *bank, int first, int last)
+{
+ int ret, i;
+
+ if(bank->target->state != TARGET_HALTED)
+ {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ for(i = first; i <= last; i++)
+ {
+ ret = sim3x_erase_page(bank, bank->sectors[i].offset);
+ if(ERROR_OK != ret)
+ return ret;
+ }
+
+ return ERROR_OK;
+}
+
+static int sim3x_write_block(struct flash_bank *bank, uint8_t *buf,
+ uint32_t offset, uint32_t count) // count is count of half words (2
bytes)!
+{
+ struct target *target = bank->target;
+ uint32_t buffer_size = 16384;
+ struct working_area *write_algorithm;
+ struct working_area *source;
+ uint32_t address = bank->base + offset;
+ struct reg_param reg_params[5];
+ struct armv7m_algorithm armv7m_info;
+ int ret = ERROR_OK;
+
+ static const uint8_t sim3x_flash_write_code[] =
+ {
+ /* Disable erase operations (ERASEEN = 0) */
+ 0x4F, 0xF4, 0x80, 0x26, /* mov r6, #ERASEEN */
+ 0x86, 0x60, /* str r6, [r0,
#FLASHCTRL_CONFIG + BIT_CLR] */
+
+ /* Write the initial unlock value to KEY (0xA5) */
+ 0xA5, 0x26, /* movs r6,
#INITIAL_UNLOCK */
+ 0xC0, 0xF8, 0xC0, 0x60, /* str r6, [r0, #FLASHCTRL_KEY] */
+
+ /* Write the multiple unlock value to KEY (0xF2) */
+ 0xF2, 0x26, /* movs r6,
#MULTIPLE_UNLOCK */
+ 0xC0, 0xF8, 0xC0, 0x60, /* str r6, [r0, #FLASHCTRL_KEY] */
+
+/* wait_fifo: */
+ 0x16, 0x68, /* ldr r6, [r2, #0]
*/
+ 0x00, 0x2E, /* cmp r6, #0 */
+ 0x16, 0xD0, /* beq exit */
+ 0x55, 0x68, /* ldr r5, [r2, #4]
*/
+ 0xB5, 0x42, /* cmp r5, r6 */
+ 0xF9, 0xD0, /* beq wait_fifo */
+
+ /* wait for BUSYF flag */
+/* wait_busy: */
+ 0x06, 0x68, /* ldr r6, [r0,
#FLASHCTRL_CONFIG] */
+ 0x16, 0xF4, 0x80, 0x1F, /* tst r6, #BUSYF */
+ 0xFB, 0xD1, /* bne wait_busy */
+
+ /* Write the destination address to WRADDR */
+ 0xC0, 0xF8, 0xA0, 0x40, /* str r4, [r0, #FLASHCTRL_WRADDR]
*/
+
+ /* Write the data half-word to WRDATA in right-justified format
*/
+ 0x2E, 0x88, /* ldrh r6, [r5] */
+ 0xC0, 0xF8, 0xB0, 0x60, /* str r6, [r0, #FLASHCTRL_WRDATA]
*/
+
+ 0x02, 0x35, /* adds r5, #2 */
+ 0x02, 0x34, /* adds r4, #2 */
+
+ /* wrap rp at end of buffer */
+ 0x9D, 0x42, /* cmp r5, r3 */
+ 0x01, 0xD3, /* bcc no_wrap */
+ 0x15, 0x46, /* mov r5, r2 */
+ 0x08, 0x35, /* adds r5, #8 */
+
+/* no_wrap: */
+ 0x55, 0x60, /* str r5, [r2, #4]
*/
+ 0x49, 0x1E, /* subs r1, r1, #1 */
+ 0x00, 0x29, /* cmp r1, #0 */
+ 0x00, 0xD0, /* beq exit */
+ 0xE5, 0xE7, /* b wait_fifo */
+
+/* exit: */
+ 0x5A, 0x26, /* movs r6,
#MULTIPLE_LOCK */
+ 0xC0, 0xF8, 0xC0, 0x60, /* str r6, [r0, #FLASHCTRL_KEY] */
+ 0x00, 0xBE /* bkpt #0 */
+ };
+
+ /* flash write code */
+ if(target_alloc_working_area(target, sizeof(sim3x_flash_write_code),
+ &write_algorithm) != ERROR_OK)
+ {
+ LOG_WARNING("no working area available, can't do block memory
writes");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+
+ ret = target_write_buffer(target, write_algorithm->address,
+ sizeof(sim3x_flash_write_code),
+ (uint8_t *)sim3x_flash_write_code);
+ if(ret != ERROR_OK)
+ return ret;
+
+ /* memory buffer */
+ while( target_alloc_working_area_try(target, buffer_size, &source) !=
ERROR_OK )
+ {
+ buffer_size /= 2;
+ buffer_size &= ~1UL; /* Make sure it's 2 byte aligned */
+ if (buffer_size <= 256)
+ {
+ /* we already allocated the writing code, but failed to
get a
+ * buffer, free the algorithm */
+ target_free_working_area(target, write_algorithm);
+
+ LOG_WARNING("no large enough working area available,
can't do block memory writes");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+ }
+
+ init_reg_param(®_params[0], "r0", 32, PARAM_OUT); /* flash base */
+ init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* count */
+ init_reg_param(®_params[2], "r2", 32, PARAM_OUT); /* buffer start
*/
+ init_reg_param(®_params[3], "r3", 32, PARAM_OUT); /* buffer end */
+ init_reg_param(®_params[4], "r4", 32, PARAM_IN_OUT); /* target
address */
+
+ buf_set_u32(reg_params[0].value, 0, 32,
(uint32_t)&FLASHCTRL0_CONFIG->all);
+ buf_set_u32(reg_params[1].value, 0, 32, count);
+ buf_set_u32(reg_params[2].value, 0, 32, source->address);
+ buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
+ buf_set_u32(reg_params[4].value, 0, 32, address);
+
+ armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
+ armv7m_info.core_mode = ARM_MODE_THREAD;
+
+ ret = target_run_flash_async_algorithm(target, buf, count, 2,
+ 0, NULL,
+ 5, reg_params,
+ source->address, source->size,
+ write_algorithm->address, 0,
+ &armv7m_info);
+
+ if(ret == ERROR_FLASH_OPERATION_FAILED)
+ {
+ LOG_ERROR("flash write failed at address 0x%"PRIx32,
+ buf_get_u32(reg_params[4].value, 0, 32));
+ }
+
+ target_free_working_area(target, source);
+ target_free_working_area(target, write_algorithm);
+
+ destroy_reg_param(®_params[0]);
+ destroy_reg_param(®_params[1]);
+ destroy_reg_param(®_params[2]);
+ destroy_reg_param(®_params[3]);
+ destroy_reg_param(®_params[4]);
+
+ return ret;
+}
+
+static int sim3x_flash_write(struct flash_bank *bank, uint8_t * buffer,
uint32_t offset, uint32_t count)
+{
+ int ret;
+ Sim3x_info * sim3x_info;
+ struct target * target;
+ uint8_t *new_buffer = NULL;
+
+ target = bank->target;
+ if(target->state != TARGET_HALTED)
+ {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ sim3x_info = bank->driver_priv;
+
+ if(offset & 0x1)
+ {
+ LOG_ERROR("offset 0x%" PRIx32 " breaks required 2-byte
alignment", offset);
+ return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
+ }
+
+ if (count & 0x1)
+ {
+ uint32_t old_count = count;
+ count++;
+ new_buffer = malloc(count);
+
+ if(new_buffer == NULL)
+ {
+ LOG_ERROR("odd number of bytes to write and no memory "
+ "for padding buffer");
+ return ERROR_FAIL;
+ }
+ LOG_INFO("odd number of bytes to write (%d), extending to %d "
+ "and padding with 0xff", old_count, count);
+
+ memset(buffer, 0xff, count);
+ buffer = memcpy(new_buffer, buffer, old_count);
+ }
+
+ uint32_t half_words_remaining = count / 2;
+
+ ret = sim3x_write_block(bank, buffer, offset, half_words_remaining);
+
+ if (new_buffer)
+ free(new_buffer);
+
+ return ret;
+}
+
+static int sim3x_flash_protect(struct flash_bank *bank, int set, int first,
int last)
+{
+ int ret;
+ uint32_t lock_word_offset;
+ Uu32 lock_word_number;
+ uint8_t * buffer;
+ Sim3x_info * sim3x_info;
+ struct target * target;
+
+ target = bank->target;
+ if(target->state != TARGET_HALTED)
+ {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ sim3x_info = bank->driver_priv;
+
+ lock_word_number.u32 = 0xFFFFFFFE;
+ ret = ERROR_OK;
+ buffer = NULL;
+ switch(sim3x_info->flash_locked)
+ {
+ case 0:
+ buffer = malloc(4);
+ buffer[0] = lock_word_number.u8[0];
+ buffer[1] = lock_word_number.u8[1];
+ buffer[2] = lock_word_number.u8[2];
+ buffer[3] = lock_word_number.u8[3];
+
+ ret = sim3x_flash_write(bank, buffer, LOCK_WORD, 4);
+ if(ERROR_OK != ret)
+ break;
+
+ LOG_INFO("Flash locked");
+ break;
+
+ case 1:
+ LOG_INFO("Flash is already locked");
+ break;
+
+ case -1: // Lock word is 0x00000000 and can not be set without erase
+ buffer = malloc(sim3x_info->flash_page_size);
+ lock_word_offset = LOCK_WORD % sim3x_info->flash_page_size;
+
+ ret = target_read_buffer(target, LOCK_WORD - lock_word_offset,
sim3x_info->flash_page_size, buffer);
+ if(ERROR_OK != ret)
+ break;
+
+ ret = sim3x_erase_page(bank, LOCK_WORD);
+ if(ERROR_OK != ret)
+ break;
+
+ buffer[lock_word_offset] = lock_word_number.u8[0];
+ buffer[lock_word_offset + 1] = lock_word_number.u8[1];
+ buffer[lock_word_offset + 2] = lock_word_number.u8[2];
+ buffer[lock_word_offset + 3] = lock_word_number.u8[3];
+
+ ret = sim3x_flash_write(bank, buffer, LOCK_WORD -
lock_word_offset, sim3x_info->flash_page_size);
+ if(ERROR_OK != ret)
+ break;
+
+ LOG_INFO("Page with Lock word was erased and again written");
+ LOG_INFO("Flash locked");
+ break;
+ }
+
+ if(buffer)
+ free(buffer);
+
+ return ret;
+}
+
+static int sim3x_setDebugMode(struct flash_bank *bank)
+{
+ int ret;
+ struct target * target;
+
+ target = bank->target;
+/*
+ // Software Reset
+ ret = target_write_u32(target, (uint32_t)&RSTSRC0_RESETEN->set,
RSTSRC0_RESETEN_SWREN_MASK);
+ if(ERROR_OK != ret)
+ return ret;
+
+ alive_sleep(1);
+
+ ret = target_halt(target);
+ if(ERROR_OK != ret)
+ return ret;
+*/
+ // Disable watchdog timer
+ ret = target_write_u32(target, WDTIMER0_WDTKEY, WDTIMER0_KEY_ATTN);
+ if(ERROR_OK != ret)
+ return ret;
+
+ ret = target_write_u32(target, WDTIMER0_WDTKEY, WDTIMER0_KEY_DISABLE);
+ if(ERROR_OK != ret)
+ return ret;
+
+ // Enable one write command
+ ret = target_write_u32(target, WDTIMER0_WDTKEY, WDTIMER0_KEY_ATTN);
+ if(ERROR_OK != ret)
+ return ret;
+
+ ret = target_write_u32(target, WDTIMER0_WDTKEY, WDTIMER0_KEY_WRITE);
+ if(ERROR_OK != ret)
+ return ret;
+
+ // Watchdog Timer Debug Mode
+ ret = target_write_u32(target, (uint32_t)&WDTIMER0_CONTROL->set,
WDTIMER0_CONTROL_DBGMD_MASK);
+ if(ERROR_OK != ret)
+ return ret;
+
+ // Enable VDD Supply Monitor and set as a reset source
+ ret = target_write_u32(target, (uint32_t)&VMON0_CONTROL->set,
VMON0_CONTROL_VMONEN_MASK);
+ if(ERROR_OK != ret)
+ return ret;
+
+ ret = target_write_u32(target, (uint32_t)&RSTSRC0_RESETEN->set,
RSTSRC0_RESETEN_VMONREN_MASK);
+ if(ERROR_OK != ret)
+ return ret;
+
+ // Flash Controller Clock Enable
+ ret = target_write_u32(target, (uint32_t)&CLKCTRL0_APBCLKG0->set,
CLKCTRL0_APBCLKG0_FLCTRLCEN_MASK);
+ if(ERROR_OK != ret)
+ return ret;
+
+ return ERROR_OK;
+}
+
+static int sim3x_device_probe(struct flash_bank *bank)
+{
+ int ret, i, num_pages;
+ Sim3x_info * sim3x_info;
+
+ sim3x_info = bank->driver_priv;
+ sim3x_info->probed = 0;
+
+ ret = sim3x_setDebugMode(bank);
+ if(ERROR_OK != ret)
+ return ret;
+
+ ret = sim3x_read_info(bank);
+ if(ERROR_OK != ret)
+ return ret;
+/*
+ switch(sim3x_info->part_family)
+ {
+ case 'c':
+ case 'C':
+ LOG_INFO("SiM3Cx detected");
+ break;
+
+ case 'u':
+ case 'U':
+ LOG_INFO("SiM3Ux detected");
+ break;
+
+ case 'l':
+ case 'L':
+ LOG_INFO("SiM3Lx detected");
+ break;
+
+ default:
+ LOG_ERROR("Unsupported MCU family %c", sim3x_info->part_family);
+ return ERROR_FAIL;
+ }
+
+ LOG_INFO("flash size = %dKB", sim3x_info->flash_size_KB);
+ LOG_INFO("flash page size = %dB", sim3x_info->flash_page_size);
+*/
+ num_pages = sim3x_info->flash_size_KB * 1024 /
sim3x_info->flash_page_size;
+
+ if(bank->sectors)
+ {
+ free(bank->sectors);
+ bank->sectors = NULL;
+ }
+
+ bank->base = FLASH_BASE_ADDRESS;
+ bank->size = num_pages * sim3x_info->flash_page_size;
+ bank->num_sectors = num_pages;
+ bank->sectors = malloc( sizeof(struct flash_sector) * num_pages );
+
+ for(i = 0; i < num_pages; i++)
+ {
+ bank->sectors[i].offset = i * sim3x_info->flash_page_size;
+ bank->sectors[i].size = sim3x_info->flash_page_size;
+ bank->sectors[i].is_erased = -1;
+ bank->sectors[i].is_protected = sim3x_info->flash_locked > 0;
+ }
+
+ sim3x_info->probed = 1;
+
+ return ERROR_OK;
+}
+
+static int sim3x_probe(struct flash_bank *bank)
+{
+ return sim3x_device_probe(bank);
+}
+
+static int sim3x_auto_probe(struct flash_bank *bank)
+{
+ if( ( (Sim3x_info *)bank->driver_priv )->probed )
+ return ERROR_OK;
+
+ return sim3x_device_probe(bank);
+}
+
+static int sim3x_flash_protect_check(struct flash_bank *bank)
+{
+ int ret, i;
+
+ if(bank->target->state != TARGET_HALTED)
+ {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ ret = sim3x_flash_lock_check(bank);
+ if(ERROR_OK != ret)
+ return ret;
+
+ for (i = 0; i < bank->num_sectors; i++)
+ bank->sectors[i].is_protected = ( (Sim3x_info
*)bank->driver_priv )->flash_locked > 0;
+
+ return ERROR_OK;
+}
+
+static int sim3x_flash_info(struct flash_bank *bank, char *buf, int buf_size)
+{
+ int ret;
+ //int printed = 0;
+ //Sim3x_info * sim3x_info;
+
+ ret = sim3x_read_info(bank);
+ if(ERROR_OK != ret)
+ return ret;
+
+ snprintf(buf, buf_size, "SiM3x");
+/*
+ sim3x_info = bank->driver_priv;
+
+ // Part
+ printed = snprintf(buf, buf_size, "SiM3%c%d", sim3x_info->part_family,
sim3x_info->part_number);
+ buf += printed;
+ buf_size -= printed;
+
+ if(buf_size <= 0)
+ return ERROR_BUF_TOO_SMALL;
+
+ // Package
+ printed = snprintf(buf, buf_size, "-%c-%s",
sim3x_info->device_package[0], sim3x_info->device_package + 1);
+ buf += printed;
+ buf_size -= printed;
+
+ if(buf_size <= 0)
+ return ERROR_BUF_TOO_SMALL;
+
+ // Revision
+ if(sim3x_info->device_revision <= 'Z' - 'A')
+ {
+ printed = snprintf(buf, buf_size, " - Rev: %c",
sim3x_info->device_revision + 'A');
+ buf += printed;
+ buf_size -= printed;
+
+ if(buf_size <= 0)
+ return ERROR_BUF_TOO_SMALL;
+ }
+*/
+ return ERROR_OK;
+}
+
+static const struct command_registration sim3x_exec_command_handlers[] =
+{
+ COMMAND_REGISTRATION_DONE
+};
+
+static const struct command_registration sim3x_command_handlers[] =
+{
+ {
+ .name = "sim3x",
+ .mode = COMMAND_ANY,
+ .help = "sim3x flash command group",
+ .usage = "",
+ .chain = sim3x_exec_command_handlers,
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+struct flash_driver sim3x_flash =
+{
+ .name = "sim3x",
+ .commands = sim3x_command_handlers,
+ .flash_bank_command = sim3x_flash_bank_command,
+ .erase = sim3x_flash_erase,
+ .protect = sim3x_flash_protect,
+ .write = sim3x_flash_write,
+ .read = default_flash_read,
+ .probe = sim3x_probe,
+ .auto_probe = sim3x_auto_probe,
+ .erase_check = default_flash_blank_check,
+ .protect_check = sim3x_flash_protect_check,
+ .info = sim3x_flash_info
+};
diff --git a/tcl/target/sim3x_stlink.cfg b/tcl/target/sim3x_stlink.cfg
new file mode 100755
index 0000000..28fc345
--- /dev/null
+++ b/tcl/target/sim3x_stlink.cfg
@@ -0,0 +1,27 @@
+#
+# Silicon Laboratories SiM3x Cortex-M3
+#
+
+set CHIPNAME SiM3x
+set CPUTAPID 0x2BA01477
+set CPURAMSIZE 0x8000
+set CPUROMSIZE 0x40000
+
+set _TRANSPORT hla_swd
+set _CHIPNAME $CHIPNAME
+set _CPUTAPID $CPUTAPID
+set _WORKAREASIZE $CPURAMSIZE
+set _CPUROMSIZE $CPUROMSIZE
+
+adapter_nsrst_delay 200
+
+transport select $_TRANSPORT
+hla newtap $_CHIPNAME cpu -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME hla_target -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size
$_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME sim3x 0 $_CPUROMSIZE 0 0 $_TARGETNAME
--
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