Perhaps this is relevant here?
https://github.com/riscv-collab/riscv-openocd/issues/1113
Hello,
Let's assume the debugger uses the direct system bus access to set a software
breakpoint on address 'A', which means it temporarily write an 'EBREAK' into
the data memory at address 'A', but the core may has already cached the memory
data 'X' of an address 'A' in the data cache. In order
Hello,
Let's assume the debugger uses the direct system bus access to set a software
breakpoint on address 'A', which means it temporarily write an 'EBREAK' into
the data memory at address 'A', but the core may has already cached the memory
data 'X' of an address 'A' in the data cache. In order
