Merged.
Thanks!
--
Øyvind Harboe
Can Zylin Consulting help on your project?
US toll free 1-866-980-3434 / International +47 51 63 25 00
http://www.zylin.com/zy1000.html
ARM7 ARM9 ARM11 XScale Cortex
JTAG debugger and flash programmer
___
Merged.
Thanks!
--
Øyvind Harboe
Can Zylin Consulting help on your project?
US toll free 1-866-980-3434 / International +47 51 63 25 00
http://www.zylin.com/zy1000.html
ARM7 ARM9 ARM11 XScale Cortex
JTAG debugger and flash programmer
___
merged.
Thanks!
--
Øyvind Harboe
Can Zylin Consulting help on your project?
US toll free 1-866-980-3434 / International +47 51 63 25 00
http://www.zylin.com/zy1000.html
ARM7 ARM9 ARM11 XScale Cortex
JTAG debugger and flash programmer
___
How's this one coming?
--
Øyvind Harboe
Can Zylin Consulting help on your project?
US toll free 1-866-980-3434 / International +47 51 63 25 00
http://www.zylin.com/zy1000.html
ARM7 ARM9 ARM11 XScale Cortex
JTAG debugger and flash programmer
___
On Sat, Dec 4, 2010 at 9:52 AM, Freddie Chopin freddie_cho...@op.pl wrote:
On 2010-12-04 09:40, Øyvind Harboe wrote:
Merged.
Thanks!
You know that this does not work the intended way
without the new version of lpc2478.cfg file?
Ah, right. It doesn't break any old config scripts, so I'll
On 2010-12-04 00:00, Michael Schwingen wrote:
On 12/03/2010 11:11 PM, Freddie Chopin wrote:
How can this be unreliable? LPC23xx/LPC24xx after reset use 4MHz
internal clock. Doing reset halt sets that clock and prevents any
code from changing that (let's not talk about broken cases, because a
On 2010-12-04 00:32, Rolf Meeser wrote:
This is a misconception. When OpenOCD tries to take control after a
reset, the CPU is already running. ISP mode or existing user firmware
may or may not have changed the clock tree. Like it or not, but there is
no a priori knowledge of CPU clock.
When
Hi everyone,
Ah, I should have added that voltage was the very first thing I
checked. On the S5PC100 the JTAG runs at VDD_EXT which has a valid
operating range from below 1.8V to above 3.3V, and the board I'm
trying to bring up has VDD_EXT set to 3.3V (as designed, measured to
~3.25V), so
On 12/04/2010 10:31 AM, Freddie Chopin wrote:
On 2010-12-04 00:32, Rolf Meeser wrote:
This is a misconception. When OpenOCD tries to take control after a
reset, the CPU is already running. ISP mode or existing user firmware
may or may not have changed the clock tree. Like it or not, but there
On 12/04/2010 10:02 AM, Øyvind Harboe wrote:
also that name is very long compared to other names. I care
about that because I have names in a dropdownlist on ZY1000 :-)
Feel free to change embedded-artists into ea!
Not every company name can be as compact as Zylin :-)
On 2010-12-04 12:05, Rolf Meeser wrote:
When doing reset halt (which would halt the chip immediately after
reset) the clock would be 4MHz.
Wrong. I've explained that often enough.
So you say that after reset and immediate halt the chip clock (for new
LPCs) is not 4MHz? Are you working for
On 2010-12-04 12:05, Rolf Meeser wrote:
For me this policy is right. I'm willing to state this on as many
occasions as required.
Speaking about this right/wrong policy - it's said that reset_config
does not belong to target config files, yet you haven't changed that,
but left these wrong
On 12/04/2010 12:35 PM, Freddie Chopin wrote:
On 2010-12-04 12:05, Rolf Meeser wrote:
For me this policy is right. I'm willing to state this on as many
occasions as required.
Speaking about this right/wrong policy - it's said that reset_config
does not belong to target config files, yet you
On 4.12.2010 13:35, Freddie Chopin wrote:
Speaking about this right/wrong policy - it's said that reset_config
does not belong to target config files, yet you haven't changed that,
but left these wrong command there... How come?
Funny thing, each time I recall a discussion about LPC2xxx
Definitely my last post on this thread.
On 12/04/2010 12:33 PM, Freddie Chopin wrote:
On 2010-12-04 12:05, Rolf Meeser wrote:
When doing reset halt (which would halt the chip immediately after
reset) the clock would be 4MHz.
Wrong. I've explained that often enough.
So you say that after
On 2010-12-04 13:59, Rolf Meeser wrote:
Definitely my last post on this thread.
If that's the case then there's no need to reply...
4\/3!!
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On 2010-12-04 13:59, Rolf Meeser wrote:
Definitely my last post on this thread.
On 12/04/2010 12:33 PM, Freddie Chopin wrote:
On 2010-12-04 12:05, Rolf Meeser wrote:
When doing reset halt (which would halt the chip immediately after
reset) the clock would be 4MHz.
Wrong. I've explained that
This is directly related to the findings from this post:
https://lists.berlios.de/pipermail/openocd-development/2010-December/017405.html
I've only removed srst_pulls_trst and comments that mentioned that (and
comments that were not very helpful)
4\/3!!
From
On Sat, Dec 4, 2010 at 10:47 PM, Freddie Chopin freddie_cho...@op.pl wrote:
This is directly related to the findings from this post:
https://lists.berlios.de/pipermail/openocd-development/2010-December/017405.html
I've only removed srst_pulls_trst and comments that mentioned that (and
Here is my vision of this patch - with default value.
4\/3!!
From f573665d0ea4afbacff730c2591cf593374097b7 Mon Sep 17 00:00:00 2001
From: Rolf Meeser rolfm_...@yahoo.de
Date: Fri, 3 Dec 2010 14:10:40 +0100
Subject: [PATCH] lpc2478 target config: CCLK as (optional) parameter
Differences to
On Wednesday 01 December 2010 19:55:23 Øyvind Harboe wrote:
On Wed, Dec 1, 2010 at 6:04 PM, Peter Stuge pe...@stuge.se wrote:
Øyvind Harboe wrote:
If iMX51 is broken and the current CortexA8 workaround code for it
breaks other CPUs, then I think that the automatic workaround code
for
On Tuesday 30 November 2010 08:16:31 Øyvind Harboe wrote:
This patch breaks debugging on the DM37x. It appears that the debug
base and APID is not sufficient to identify problematic processors
since the DM37x on the Beagleboard XM incorrectly passes the checks in
arm_adi_v5.c:
On 04.12.2010 10:08, Freddie Chopin wrote:
So you're all about correctness and you don't reset halt the chip before
flashing? How is that correct? Actually flashing does not work if you
don't reset halt the chip. The need for halting is obvious. The need
for reset is not, but think about what
On 04/12/2010, at 7:43 PM, Øyvind Harboe oyvind.har...@zylin.com wrote:
How's this one coming?
I'm happy with the previous set of patches I submitted (nov 30), it's been
working well for me for the past couple of weeks with no issues.
Andrew
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