could be 1MHz, autodetect or whatever, but all configuration scripts
are required to make decision.
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I don't subscribe to the idea that there is a safe, correct and robust
default setting for JTAG clock, better to make the user get a
good error message that points him in the right direction.
1MHz will fail on plenty of cards (with RC oscilators typically).
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Can
A starting patch, propagate error for getting speed.
In the future it will fail when no jtag speed has been set
before someone queries the speed.
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More generally, if there is something that user must specify
that he hasn't and the script is working by chance, then it
would be great if we could robustly detect this situation and
require the user to specify that option.
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On Sun, Dec 5, 2010 at 5:43 PM, David Brownell wrote:
>
>
> --- On Sun, 12/5/10, Øyvind Harboe wrote:
>
>> Does anyone have any objections to
>> getting rid of the
>> concept of a default JTAG clock rate?
>
> NO. But let's see a proposed patch ...
Try with the currently committed stuff:
openocd -c "set CCLK 12345; source [find target/lpc2478.cfg]"
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in my
book that counts as not using the default clock rate.
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much appreciate the effort that you put into answering
all the questions that came up to this patch.
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try:
git add .
git commit --author="Andrew Leech "
=> type commit comment
git format-patch HEAD^
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On Sat, Dec 4, 2010 at 9:52 AM, Freddie Chopin wrote:
> On 2010-12-04 09:40, Øyvind Harboe wrote:
>>
>> Merged.
>>
>> Thanks!
>
> You know that this does not work the intended way
>without the "new" version of lpc2478.cfg file?
Ah, right. It doesn
How's this one coming?
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Merged.
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merged.
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Merged.
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Merged.
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Looks good to me.
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Will merge.
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Any objections to merging?
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You're the expert. I'll merge after cooloff.
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When I tried it, it was OK. I didn't use a dongle though,
but the ZY1000 obviously. The ZY1000 is more like the
Abatron in that it actually runs OpenOCD onboard and
thus benefits from very low latency.
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Try reducing the jtag_khz, you may be on the edge of what
works.
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You're the expert.
If I don't hear anything, I'll merge it after a cooloff on the list
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y I want source control to be treated as a hard problem, both
by tools and engineers I work with.
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Merged.
Thanks!
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On Thu, Dec 2, 2010 at 6:21 PM, Starkeeper wrote:
> How can I test if the working area is correct?
> The memorymap of my controller tells me that at address 0x4000 is a
> 64KB RAM.
mww + mdw?
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Search for "set architecture".
I'm working on a project where I'm getting too many registers
from the GDB server compared to what I need, and then
I set the architecture before I try target remote:
set architecture powerpc:common
target remote
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Any objections to this one?
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On Wed, Dec 1, 2010 at 11:00 PM, Freddie Chopin wrote:
> On 2010-12-01 22:41, Øyvind Harboe wrote:
>>
>> On Wed, Dec 1, 2010 at 10:25 PM, Freddie Chopin
>> wrote:
>>>
>>> On 2010-11-30 08:20, Øyvind Harboe wrote:
>>>>
>>>> Are the
On Wed, Dec 1, 2010 at 10:25 PM, Freddie Chopin wrote:
> On 2010-11-30 08:20, Øyvind Harboe wrote:
>>
>> Are there any patches out there that should have been
>> applied but haven't?
>
> Are you planning a release?
I'm hopeful that we can get the swd stuff fr
On Wed, Dec 1, 2010 at 6:04 PM, Peter Stuge wrote:
> Øyvind Harboe wrote:
>> If iMX51 is broken and the current CortexA8 workaround code for it
>> breaks other CPUs, then I think that the automatic workaround code
>> for iMX51 has to be either fixed or removed.
>
> Do y
.cz/r/git2cl.git
This is not a workaround, it's a solution! :-)
The only question is whether we should commit the change.
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he load command notice that
>the target address is in Flash and start the flash programming?
That's right. "load" will look at the configuration and if the memory range is
flash, then the flash is erased and programmed.
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Merged.
Thanks!
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Normally you should be able to connect and flash by:
target remote localhost:
monitor reset init
load
stepi
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Can you try with a 32 bit OpenOCD executable?
On Wed, Dec 1, 2010 at 8:35 AM, Domen Puncer wrote:
> On Tue, Nov 30, 2010 at 16:09, Øyvind Harboe wrote:
>> Could you try to reproduce this with the dummy driver?
>>
>> configure --enable-dummy ...
>>
>> openocd
a
generic mmu enable/disable (+ report status) command.
Perhaps looking at virt2phys command and implementation
would be a good start?
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Did you try "reset init" and then flash programming?
Perhaps there is some memory parameters that have to be
set up.
You did not provide a complete configuration file...
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Could you provide a log?
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Try reducing the clock speed to something ridiculously low.
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Could you try to reproduce this with the dummy driver?
configure --enable-dummy ...
openocd -c "interface dummy"
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32 vs. 64 bit problem?
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Are there any patches out there that should have been
applied but haven't?
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If iMX51 is broken and the current CortexA8 workaround code for it
breaks other CPUs, then I think that the automatic workaround code
for iMX51 has to be either fixed or removed.
Thoughts?
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}
>
> Is there another way that these problematic CPUs can be identified?
Anyone?
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Merged.
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Is there anyone on the list with experience as a release engineer for
an open source project that would like to have a stab at releasing
OpenOCD 0.5?
We need some extra hands...
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working
> for me.
Good catch!
Unfortunately that's a pretty big commit. The next thing I could
suggest in terms of bisection would be to create a working
branch and split that commit as many times as possible and
do a bisect on that branch...
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Note that I'm just a humble maintainer here. I'm not able to follow
this part of the OpenOCD conversation and you guys are
the experts.
Let me know when you all agree that the patches are ready to be merged.
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On Mon, Nov 29, 2010 at 11:12 PM, Timo Juhani Lindfors
wrote:
> Øyvind Harboe writes:
>> This patch introduces a serious and sweeping regression that
>> a compiler warning caught:
>
> Indeed. Thanks for catching this and sorry for forgetting the return.
>
>> Ho
Does anyone have any objections to committing this?
Are you the expert on this interface?
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Hi,
could you post the patches.
Thanks!
Easier to review and the way things are normally done here
on the list.
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patch?
(Otherwise the patch seems fine to me)
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Hi Rolf,
you're the expert here.
Let me know when you think the change is ready to go in.
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This is a backtrace without line numbers. Could you try to
produce a backtrace with linenumbers?
Thanks!
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2010/11/26 MIroslav Dušek :
> Hi ,
> Thank you for help.
> I am sorry, but what is openocd master branch?
0.4 is quite old. Your problem may have been long fixed.
clone the openocd git repository, check out the master branch build OpenOCD.
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How about adding a handler(to Windows and Linux) that prints out
instructions on how to track down and report a segfault?
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Try the openocd master branch.
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Does this code do this unconditionally for all flash types or only
the flash types that require it?
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e add a mirror, or kill
> it. Right now, it's not possible to bootstrap openocd.
>
> 2). Can someone email me a tarball of the jimtcl repo? Or preferably
> point me at a git mirror?
Be patient. repo.or.cz is used by thousands of people, so it will
probably be up again before lon
Merged.
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breakpoints is a key feature of OpenOCD whereas the
"bp" from the telnet is more peripheral so we want to make
sure that we don't break gdb breakpoints here.
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h
Merged.
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e.g. flash erase_address now works across an address
range that spans multiple flash chips.
Signed-off-by: Øyvind Harboe
---
src/flash/nor/core.c | 39 ++-
1 files changed, 38 insertions(+), 1 deletions(-)
diff --git a/src/flash/nor/core.c b/src/flash/nor
Signed-off-by: Øyvind Harboe
---
src/target/target.c | 22 --
1 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/src/target/target.c b/src/target/target.c
index a282aab..93efa76 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -4964,9 +4964,10
You're the expert here.
Unless I hear protests from others I intend to commit
this after a cool-off period.
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}
Before we make further changes, we'll have to find out where it broke
and how to fix it properly. The problem with the change above is that
I worry that it will break GDB breakpoints.
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Good work!
Which commit was is that actually broke this?
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the binary search?
Read "git bisect" documentation for tips.
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_
Can you try a "git bisect" ?
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ot openocd replace the actual instruction at the breakpoint ?).
Yes.
The way software breakpoints are implemented in CPUs is that the
instruction at the breakpoint address is modified to a
software breakpoint instruction. That's why software breakpoints
in flash is pretty much impractical.
On Thu, Nov 18, 2010 at 11:18 AM, 韦东山 wrote:
> Øyvind_Harboe, gdb is ok. I want to use telnet interface.
The telnet bp commands is a less trodden path I suppose.
Did you read up on the source code?
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On Thu, Nov 18, 2010 at 11:05 AM, 韦东山 wrote:
> I have try the latest master branch, the problem is the same.
Did you try from gdb?
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Please try with the latest master branch.
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Merged.
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Merged.
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+ there is the disable internal jim option if the user wants to
use something else.
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> Are you aware of any target, other than SPEAr, that provides memory
> mapping feature of SPI flash? I quickly searched, but failed.
Wow :-) The only case I know of is the ZPU which has a memory
mapped serial flash, but that's another story not relevant here.
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svf/xsvf has been a somewhat peripheral feature of OpenOCD
and I couldn't possibly comment on whether this patch should
be applied or not.
Do you feel it's ready to be applied if there are no protests?
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Merged.
It would be nice with some followup patches:
- some comments on how this code can/should be refactored rather
than copy pasted as new devices are added
- a patch to get rid of the non-sensical .h files in drivers/nor/*.h and
just put the private data into the .c file.
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A large startup.tcl is generated by the makefiles from many smaller
startup.tcl scripts around the source tree. This startup.tcl is then converted
to .c and linked into openocd. Why? Because it was felt that it was an important
feature to be able to launch openocd without a dependency on the file
On Mon, Nov 15, 2010 at 4:35 PM, Peter Stuge wrote:
> Øyvind Harboe wrote:
>> Note that if an image is too big(even if you have multiple
>> back to back chips), you'll now get an error message that
>> no flash chip is found:
>>
>> LOG_ERROR("No flash
On Mon, Nov 15, 2010 at 4:07 PM, Peter Stuge wrote:
> Øyvind Harboe wrote:
>> > there are parts of the patch which should be separated out,
>> > because they are not really specific to spearsmi.
> ..
>> > Refactor now, or then?
> ..
>> I haven't se
flash programming via flash write_image or gdb load would
produce a bogus error message that the flash chip was to
small.
The solution is to limit the current flash programming
run to the current chip.
Signed-off-by: Øyvind Harboe
---
src/flash/nor/core.c | 10 +++---
1 files changed, 7
Note that if an image is too big(even if you have multiple
back to back chips), you'll now get an error message that
no flash chip is found:
LOG_ERROR("No flash at address 0x%08" PRIx32 "\n", addr);
--
Øyvind Harboe
Can Zylin Consulting help on your project?
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On Sat, Nov 13, 2010 at 1:09 PM, Peter Stuge wrote:
> Øyvind Harboe wrote:
>> So basically if OpenOCD had some generic support for
>> interfacing to SPI chips via the target CPU over JTAG,
>> then you could build on that for your flash driver?
>>
>> That seems
On Sat, Nov 13, 2010 at 10:17 AM, Øyvind Harboe wrote:
> Going twice...
Merged.
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Øyvind Harboe
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ARM7 ARM9 ARM11 XScale Cortex
JTAG debugger and fl
>
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>
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Can Zylin Consulting
On Mon, Nov 15, 2010 at 8:37 AM, Domen Puncer wrote:
> On Sat, Nov 13, 2010 at 13:08, Øyvind Harboe wrote:
>> Does the attached patch fix the problem?
>
> Jup, did the trick.
Merged.
Thanks for testing & excellent reporting!
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Øyvind Harboe
Can Zylin Consulting help o
On Sun, Nov 14, 2010 at 10:58 PM, Freddie Chopin wrote:
> On 2010-11-14 18:49, Øyvind Harboe wrote:
>>
>> The problem is that the target is crashing while executing the programming
>> algorithm, so it never completes.
>
> You mean crashing like having Hard Fault excep
> As I cannot reproduce, if this one is repeating at your side, maybe try
> injecting some messages around there to see whether that's the exact point
> of problems?
The problem is that the target is crashing while executing the programming
algorithm, so it never completes.
--
>> Perhaps sharper error messages?
>
> It was in the previous code:
>
> - tst r3, #0x14
> - bne exit
k. I missed that one.
Unless I hear protests, I'll merge this code after a cool off period.
--
Øyvind Harboe
Can Zylin Consulting
On Sat, Nov 13, 2010 at 11:14 PM, Freddie Chopin wrote:
> On 2010-11-13 16:47, Øyvind Harboe wrote:
>>
>> Is it conceivable that this would address the block
>> flash programming problems I saw the other day
>> and you were not able to reproduce?
>
> Rather not..
Is it conceivable that this would address the block
flash programming problems I saw the other day
and you were not able to reproduce?
--
Øyvind Harboe
Can Zylin Consulting help on your project?
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ARM7
Does the attached patch fix the problem?
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Øyvind Harboe
Can Zylin Consulting help on your project?
US toll free 1-866-980-3434 / International +47 51 63 25 00
http://www.zylin.com/zy1000.html
ARM7 ARM9 ARM11 XScale Cortex
JTAG debugger and flash programmer
From
factoring out some code from
your flash driver.
It would be nice to have two or three flash drivers doing this so
we can start seeing what it would make sense to
have in the common API.
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Øyvind Harboe
Can Zylin Consulting help on your project?
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e
assuring that such databases are up to date. They do for
Keil, IAR and their ilk.
--
Øyvind Harboe
Can Zylin Consulting help on your project?
US toll free 1-866-980-3434 / International +47 51 63 25 00
http://www.zylin.com/zy1000.html
ARM7 ARM9 ARM11 XScale Cortex
JTAG debugger and flash
Has anyone taken this plugin for a spin?
It displays peripheral registers and there are databases for some
common CPUs built in.
http://sourceforge.net/projects/embsysregview/
--
Øyvind Harboe
Can Zylin Consulting help on your project?
US toll free 1-866-980-3434 / International +47 51 63 25
Going twice...
--
Øyvind Harboe
Can Zylin Consulting help on your project?
US toll free 1-866-980-3434 / International +47 51 63 25 00
http://www.zylin.com/zy1000.html
ARM7 ARM9 ARM11 XScale Cortex
JTAG debugger and flash programmer
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