Hi all,
Can't enter debug state as setting cortex-a8 register of DRCR as below ,Any
idea?
> mww 0x54011090 1
setting DRCR halt request bit
> mdw 0x54011088
0x54011088 4b072002. .K
reading DSCR,but core still restarted
Best Regards,
Ray
___
Magnus Lundin wrote:
> Now compare the reported start addresses below with table 5-105 in
> OMAP35x TRM, SPRUF98B–September 2008,
> and table 2-3 in CoreSight Components, and the management registers in
>
>>> dap info 1
>> ap identification register 0x04770002
>> Type is mem-ap APB
>> ap debugbas
Now compare the reported start addresses below with table 5-105 in
OMAP35x TRM, SPRUF98B–September 2008,
and table 2-3 in CoreSight Components, and the management registers in
> > dap info 1
> ap identification register 0x04770002
> Type is mem-ap APB
> ap debugbase 0x8000
> ROM table in leg
Magnus Lundin wrote:
> Dirk Behme wrote:
>> Magnus Lundin wrote:
>>> Hi
>>>
>>> There are some problems with dap info, but it seems the results are
>>> useful anyway.
>>> Her comes my interpretation:
> dap info 0
ap debugbase 0x
ap identification register 0x14770001
Dirk Behme wrote:
> Magnus Lundin wrote:
>> Hi
>>
>> There are some problems with dap info, but it seems the results are
>> useful anyway.
>> Her comes my interpretation:
>>> > dap info 0
>>> ap debugbase 0x
>>> ap identification register 0x14770001
>>> No ROM table present
>> This
Magnus Lundin wrote:
> Hi
>
> There are some problems with dap info, but it seems the results are
> useful anyway.
> Her comes my interpretation:
>> > dap info 0
>> ap debugbase 0x
>> ap identification register 0x14770001
>> No ROM table present
> This is a MEM-AP port AHB bus w
Hi
There are some problems with dap info, but it seems the results are
useful anyway.
Her comes my interpretation:
> > dap info 0
> ap debugbase 0x
> ap identification register 0x14770001
> No ROM table present
This is a MEM-AP port AHB bus with no ROM table. This could be the
Hi Dirk,
Dirk Behme skrev:
> Hi Magnus,
>
> Magnus Lundin wrote:
>> That looks very interesting.
>>
>> Here is a new patch against head that should give very much
>> information. It is tested on a STM32 CortexM3.
>> Looking at the code you can se how I think we must read the ROMTABLE
>> informat
Hi Magnus,
Magnus Lundin wrote:
> That looks very interesting.
>
> Here is a new patch against head that should give very much information.
> It is tested on a STM32 CortexM3.
> Looking at the code you can se how I think we must read the ROMTABLE
> information structure.
>
> The command syntax
That looks very interesting.
Here is a new patch against head that should give very much information.
It is tested on a STM32 CortexM3.
Looking at the code you can se how I think we must read the ROMTABLE
information structure.
The command syntax is now
>dap info n
>dap select n
If there a
Hi Magnus,
Magnus Lundin wrote:
> So there is two taps configured and no target.
> So we must configure a target, cortex_m3, attached to the omap3.cpu tap
>
> That should be:
>
> set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
> target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position
So there is two taps configured and no target.
So we must configure a target, cortex_m3, attached to the omap3.cpu tap
That should be:
set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position
$_TARGETNAME
or simply
target create omap3.c
Magnus Lundin wrote:
> Hi
>
> I think yuo can use something like:
>
> targets omap3.cpu
Doesn't work:
-- cut --
> targets omap3.cpu
Target: omap3.cpu unknown, try one of:
CmdNameType Endian AbsChainPos Name State
-- -- -- -- ---
Hi
I think yuo can use something like:
targets omap3.cpu
cortex_m3 dap 0
I have never used any target with multiple taps so this is just guessing
from my side.
Regards,
Magnus
Dirk Behme wrote:
> Magnus Lundin wrote:
>> Hi
>>
>> The following patch is a first step towards support for sevar
Magnus Lundin wrote:
> Hi
>
> The following patch is a first step towards support for sevaral AP in
> one dap.
>
> - Adds a apsel variable, corresponding to the corresponding field in the
> DP SELECT register, to the swjdap structure.
> - adds a function swjdp_apselect(swjdp_common_t *swjdp,u8
The reasons
First there is no support for interactive commands in cortex_swjdp.c,
and ther should not be any. All commands use a swjdp structure for
state information. This structure is owned by the target device
structure, in our case the cortex_m3 target type so that is the natural
place f
On Apr 14, 2009, at 12:13 PM, Magnus Lundin wrote:
Hi
The following patch is a first step towards support for sevaral AP
in one dap.
- Adds a apsel variable, corresponding to the corresponding field in
the DP SELECT register, to the swjdap structure.
- adds a function swjdp_apselect(swjd
Hi
The following patch is a first step towards support for sevaral AP in
one dap.
- Adds a apsel variable, corresponding to the corresponding field in the
DP SELECT register, to the swjdap structure.
- adds a function swjdp_apselect(swjdp_common_t *swjdp,u8 apsel) to set
this variable.
- ad
On Apr 12, 2009, at 12:13 AM, Dirk Behme wrote:
Rick Altherr wrote:
...
it looks like the following major projects are in progress:
...
- Cortex-A8 support
... has had some initial discovery but no real development.
Yes, I agree.
I'd really like to help with Cortex-A8 support. But I have
Rick Altherr wrote:
...
> it looks like the
> following major projects are in progress:
>
...
> - Cortex-A8 support
>
> ... has had
> some initial discovery but no real development.
Yes, I agree.
I'd really like to help with Cortex-A8 support. But I have to admit
that I don't understand a lo
20 matches
Mail list logo
