com>>; zhuli
<zhul...@huawei.com<mailto:zhul...@huawei.com>>;
bao.yum...@zte.com.cn<mailto:bao.yum...@zte.com.cn>;
xiaodong...@tencent.com<mailto:xiaodong...@tencent.com>;
kong.w...@zte.com.cn<mailto:kong.w...@zte.com.cn>;
li.xia...@zte.com.cn<mailto:li.xia...@zte.
u.com>;
> Justin Kilpatrick <jkilp...@redhat.com>; Ranganathan, Shobha <
> shobha.ranganat...@intel.com>; zhuli <zhul...@huawei.com>;
> bao.yum...@zte.com.cn; xiaodong...@tencent.com; kong.w...@zte.com.cn;
> li.xia...@zte.com.cn; Feng, Shaohe <shaohe.f...@inte
...@vn.fujitsu.com>; Justin Kilpatrick <jkilp...@redhat.com>;
Ranganathan, Shobha <shobha.ranganat...@intel.com>; zhuli <zhul...@huawei.com>;
bao.yum...@zte.com.cn; xiaodong...@tencent.com; kong.w...@zte.com.cn;
li.xia...@zte.com.cn; Feng, Shaohe <shaohe.f...@intel.com&
Now I am working on an FPGA management POC with Dolpher.
We have finished some code, and have discussion with Li Liu and some cyborg
developer guys.
Here are some discussions:
image management
1. User should upload the FPGA image to glance and set the tags as follow:
There are two suggestions
