On Tue, May 9, 2017 at 12:52 AM, Florian Fainelli wrote:
> On 05/08/2017 02:16 PM, Tom Psyborg wrote:
>> Is it ever going to be added so this endless spam can end?
>
> It's the first iteration of the (S)ATA patchset, and if you are not
> interested, just ignore the thread.
I mailed with Tom and i
On 05/08/2017 02:16 PM, Tom Psyborg wrote:
> Is it ever going to be added so this endless spam can end?
It's the first iteration of the (S)ATA patchset, and if you are not
interested, just ignore the thread.
Linus is doing everyone a great favor here by making sure that this
platform gets properl
On Mon, May 8, 2017 at 11:24 PM, Rob Herring wrote:
>> +Example:
>> +
>> +syscon: syscon@4000 {
>> + compatible = "cortina,gemini-syscon",
>> "cortina,gemini-clock-controller",
>> +"syscon", "simple-mfd";
>
> There are no child nodes, so you don't need simple-mfd.
Is it ever going to be added so this endless spam can end?
On 8 May 2017 at 22:07, Linus Walleij wrote:
> This is a simple reset controller in a single 32bit
> register.
>
> Signed-off-by: Linus Walleij
> ---
> ChangeLog v1->v2:
> - Move the reset controller node to be the same as the syscon
>
Is it ever going to be added so this endless spam can end?
On 8 May 2017 at 22:11, Linus Walleij wrote:
> This adds device tree bindings and a header for the Gemini SoC
> Clock Controller.
>
> Signed-off-by: Linus Walleij
> ---
> ChangeLog v1->v2:
> - Move the clock controller to be directly i
Is it ever going to be added so this endless spam can end?
On 8 May 2017 at 22:33, Linus Walleij wrote:
> On Mon, May 8, 2017 at 12:49 PM, Bartlomiej Zolnierkiewicz
> wrote:
> > On Saturday, May 06, 2017 02:10:51 PM Linus Walleij wrote:
>
> >> + Mode 3: ata0 master <-> sata0
> >> + a
Is it ever going to be added so this endless spam can end?
On 8 May 2017 at 22:12, Linus Walleij wrote:
> The Cortina Systems Gemini (SL3516/CS3516) has an on-chip clock
> controller that derive all clocks from a single crystal, using some
> documented and some undocumented PLLs, half dividers,
On Mon, May 8, 2017 at 12:49 PM, Bartlomiej Zolnierkiewicz
wrote:
> On Saturday, May 06, 2017 02:10:51 PM Linus Walleij wrote:
>> + Mode 3: ata0 master <-> sata0
>> + ata1 slave <-> sata1
>
> ata0 slave?
>
>> + ata1 master and slave interfaces brought out
>> + on
On Mon, May 8, 2017 at 12:47 PM, Bartlomiej Zolnierkiewicz
wrote:
> Also for all current drivers we just put timing values (or a logic
> to calculate them from the standard ATA timings) into the driver
> itself and not device tree (as they are based on values are dictated
> by ATA standard and sh
The Cortina Systems Gemini (SL3516/CS3516) has an on-chip clock
controller that derive all clocks from a single crystal, using some
documented and some undocumented PLLs, half dividers, counters and
gates. This is a best attempt to construct a clock driver for the
clocks so at least we can gate off
This adds device tree bindings and a header for the Gemini SoC
Clock Controller.
Signed-off-by: Linus Walleij
---
ChangeLog v1->v2:
- Move the clock controller to be directly in the parent syscon
node.
---
.../clock/cortina,gemini-clock-controller.txt | 22
include/dt-bin
The Cortina Systems Gemini reset controller is a simple
32bit register with self-deasserting reset lines. It is
accessed using regmap over syscon.
Signed-off-by: Linus Walleij
---
ChangeLog v1->v2:
- Add an explicit GPL license statement.
- Move the reset controller to be identical to the sycon
This is a simple reset controller in a single 32bit
register.
Signed-off-by: Linus Walleij
---
ChangeLog v1->v2:
- Move the reset controller node to be the same as the syscon
node, no need for a specific child node.
- Add an include file with nice #defines.
---
.../bindings/reset/cortina,gemin
On Mon, May 08, 2017 at 09:19:42PM +0200, Zoltan HERPAI wrote:
> Hi,
>
> On Mon, 8 May 2017, Daniel Engberg wrote:
>
> > Trac:
> > Is it really worth keeping trac at all? What value does it add? Just
> > display a page explaining that it's shutdown and forward to OpenWrt?
>
> There is a lot of "
Hi,
On Mon, 8 May 2017, Daniel Engberg wrote:
Trac:
Is it really worth keeping trac at all? What value does it add? Just display
a page explaining that it's shutdown and forward to OpenWrt?
There is a lot of "added value" in the tickets submitted throughout the
years, either as comments, no
On 08/05/17 15:29, David Woodhouse wrote:
On Mon, 2017-05-08 at 15:19 +0200, John Crispin wrote:
*) mailing list
- ask david to add the openwrt-adm and openwrt lists
- announce the switch to the infradead serves, asking people to
unsubscribe if they have privacy issues with this
- import the u
On 2017-05-08 15:43, Toke Høiland-Jørgensen wrote:
John Crispin writes:
Hi,
Felix, Imre and myself had 2 calls last week lasting several hours and discussed
the following proposal of conditions for a remerge that we would like to propose
and have people vote on.
Great to hear progress is be
John Crispin writes:
> Hi,
>
> Felix, Imre and myself had 2 calls last week lasting several hours and
> discussed
> the following proposal of conditions for a remerge that we would like to
> propose
> and have people vote on.
Great to hear progress is being made on this! I think the proposal l
On Mon, 2017-05-08 at 15:19 +0200, John Crispin wrote:
>
> *) mailing list
> - ask david to add the openwrt-adm and openwrt lists
> - announce the switch to the infradead serves, asking people to
> unsubscribe if they have privacy issues with this
> - import the user DB from the current openwrt a
Hi,
Felix, Imre and myself had 2 calls last week lasting several hours and
discussed the following proposal of conditions for a remerge that we
would like to propose and have people vote on.
*) branding
- the owrt side sees no option of using the lede brand
- a (minor) majority voted for ope
Hi Rafał,
I am still hoping to get confirmation from you on this patch. Is this
acceptable for upstreaming?
> Hi Rafał,
>
> > > On 03/29/2017 11:53 AM, Smith, Pieter wrote:
> > > > My apologies. I am not able to get mutt working with our corporate
> > > > infrastructure. I hope it arrives unmang
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