The R6120 has no 5GHz WLAN LED, the assigned GPIO in fact controls
the WAN LED.
Renames the LED accordingly in the device-tree.
Removes the 5GHz WLAN LED trigger.
Adds the correct WAN port LED trigger.
Currently, the MAC address for the Netgear R6120 is read from the NVRAM
partition. The of
On 2/1/19 5:32 PM, Philippe Mathieu-Daudé wrote:
> On 2/1/19 4:01 PM, Chuanhong Guo wrote:
>> Hi!
>>
>> On Fri, Feb 1, 2019 at 9:53 PM Philippe Mathieu-Daudé
>> wrote:
>>> [...]
>>> Now that you pointed this line, I am not sure it is correct...
>>> It maps I/O (0x0100) region of 1B (0 0x0
Hardware
CPU: Qualcomm Atheros QCA9561
RAM: 64M DDR2
FLASH: 16M SPI-NOR
ETH: 1x WAN - 2x LAN
WiFi: QCA9561 3T3R
BTN: 1x Reset - 1x WPS
LED: 1x Blue - 1x Red - 1x Yellow
UART: TX - GND - RX - VCC (From ethernet port)
115200n8 - 3.3V
Installation
1. Connect t
As reported in
https://forum.openwrt.org/t/ath79-image-builder-problem-for-wr842n-v1/30197/4?u=jeff
the board configuration for the ar71xx tl-wr842n-v1 improperly sets
BOARDNAME to TL-MR3420
(confirmed on master and on openwrt-18.06)
As a result, users upgrading that device to ath79 will not
On 2/1/19 4:01 PM, Chuanhong Guo wrote:
> Hi!
>
> On Fri, Feb 1, 2019 at 9:53 PM Philippe Mathieu-Daudé wrote:
>> [...]
>> Now that you pointed this line, I am not sure it is correct...
>> It maps I/O (0x0100) region of 1B (0 0x01) from PCI 0x
>> (0 0x) at 0x000 (0x000
The OpenWrt Community is proud to announce the second service release of
the stable OpenWrt 18.06 series.
OpenWrt 18.06.2 incorporates a fair number of bug fixes in the network
userland and the build system, as well as updates to the kernel and base
packages.
---
Some selected highlights of the
Hi!
On Fri, Feb 1, 2019 at 9:53 PM Philippe Mathieu-Daudé wrote:
> [...]
> Now that you pointed this line, I am not sure it is correct...
> It maps I/O (0x0100) region of 1B (0 0x01) from PCI 0x
> (0 0x) at 0x000 (0x000) into cpu space.
> But the DDR is already map
On 1/29/19 5:12 AM, Santiago Piccinini wrote:
> Tested with a dual pci QCA9558 board (LibreRouter v1) in three
> configurations: enabling pcie0 only, pcie1 only and both enabled.
>
> Signed-off-by: Santiago Piccinini
> ---
> target/linux/ath79/dts/qca9557.dtsi | 2 +-
> 1 file changed, 1 inserti
Hi Santiago,
On 1/29/19 5:12 AM, Santiago Piccinini wrote:
> Datasheet states that both PCI ranges are of 0x200 size:
> 0x1000_-0x11FF_FFF and 0x1200_-0x13FF_.
>
> Signed-off-by: Santiago Piccinini
Each PCIe root complex region is 32MB wide indeed.
> ---
> target/linux/ath79/d
Hi all,
thanks to this[0] bug report I found that the ar71xx/generic
ImageBuilder doesn't create any firmware images for profile OM2P when
used with BIN_DIR.
My first guess is that it's somewhat related to a hard coded destination
which doesn't handle BIN_DIR. At the very end of an "successful" b
Dne 01. 02. 19 v 10:51 Hauke Mehrtens napsal(a):> On 1/31/19 9:30 PM,
Mathias Kresin wrote:
>> 30/01/2019 11:38, Petr Cvek:
>>>
Hi,
thank you both for the answer and sorry for "./" in the patches I
usually do only git patching :-D. The patches are really RFC only. For
example I would like to know
On 1/31/19 9:30 PM, Mathias Kresin wrote:
> 30/01/2019 11:38, Petr Cvek:
>> Hello,
>>
>> I discovered the lantiq xrx200 lacks support for interrupts on secondary
>> VPE, and I've managed to add this functionality to the kernel, the
>> second icu controller lives on base address 0x1f880300 and works
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