Re: [PATCH] realtek: fix dell typo

2022-11-29 Thread Philippe Mathieu-Daudé
On 28/11/22 17:58, Jan-Niklas Burfeind wrote: should be add/delete or abbreviated add/del Signed-off-by: Jan-Niklas Burfeind --- .../realtek/files-5.10/drivers/net/dsa/rtl83xx/common.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH] uboot-envtools: Fix format of autogenerated sectors

2022-10-06 Thread Philippe Mathieu-Daudé
: Add support for IPQ806x AP148 and DB149") Fixes: 54b275c8ed3a ("ipq40xx: add target") Signed-off-by: Sven Eckelmann --- package/boot/uboot-envtools/files/ipq40xx | 1 + package/boot/uboot-envtools/files/ipq806x | 1 + 2 files changed, 2 insertions(+) Reviewed-by: Ph

Re: [OpenWrt-Devel] [PATCH 1/2] ath79: fix qca955x pcie0 memory size

2019-02-01 Thread Philippe Mathieu-Daudé
On 2/1/19 5:32 PM, Philippe Mathieu-Daudé wrote: > On 2/1/19 4:01 PM, Chuanhong Guo wrote: >> Hi! >> >> On Fri, Feb 1, 2019 at 9:53 PM Philippe Mathieu-Daudé >> wrote: >>> [...] >>> Now that you pointed this line, I am not sure it is correct...

Re: [OpenWrt-Devel] [PATCH 1/2] ath79: fix qca955x pcie0 memory size

2019-02-01 Thread Philippe Mathieu-Daudé
On 2/1/19 4:01 PM, Chuanhong Guo wrote: > Hi! > > On Fri, Feb 1, 2019 at 9:53 PM Philippe Mathieu-Daudé wrote: >> [...] >> Now that you pointed this line, I am not sure it is correct... >> It maps I/O (0x0100) region of 1B (0 0x01) from PCI 0x >

Re: [OpenWrt-Devel] [PATCH 2/2] ath79: fix qca955x dual pci resource allocation

2019-02-01 Thread Philippe Mathieu-Daudé
On 1/29/19 5:12 AM, Santiago Piccinini wrote: > Tested with a dual pci QCA9558 board (LibreRouter v1) in three > configurations: enabling pcie0 only, pcie1 only and both enabled. > > Signed-off-by: Santiago Piccinini > --- > target/linux/ath79/dts/qca9557.dtsi | 2 +- > 1 file changed, 1

Re: [OpenWrt-Devel] [PATCH 1/2] ath79: fix qca955x pcie0 memory size

2019-02-01 Thread Philippe Mathieu-Daudé
0 0x1000 0 > 0x0200/* pci memory */ "Map 32-bit non-prefetchable (0x0200) region of 32MB (0 0x0400) from PCI 0x1000 (0 0x1000) at 0x1000 (0x1000) into cpu space". OK, your change is correct, thus: Reviewed-by: Philippe Mathieu-Daudé >