On 2/1/19 5:32 PM, Philippe Mathieu-Daudé wrote:
> On 2/1/19 4:01 PM, Chuanhong Guo wrote:
>> Hi!
>>
>> On Fri, Feb 1, 2019 at 9:53 PM Philippe Mathieu-Daudé
>> wrote:
>>> [...]
>>> Now that you pointed this line, I am not sure it is correct...
>>> It maps I/O (0x0100) region of 1B (0
On 2/1/19 4:01 PM, Chuanhong Guo wrote:
> Hi!
>
> On Fri, Feb 1, 2019 at 9:53 PM Philippe Mathieu-Daudé wrote:
>> [...]
>> Now that you pointed this line, I am not sure it is correct...
>> It maps I/O (0x0100) region of 1B (0 0x01) from PCI 0x
>> (0 0x) at 0x000
Hi!
On Fri, Feb 1, 2019 at 9:53 PM Philippe Mathieu-Daudé wrote:
> [...]
> Now that you pointed this line, I am not sure it is correct...
> It maps I/O (0x0100) region of 1B (0 0x01) from PCI 0x
> (0 0x) at 0x000 (0x000) into cpu space.
> But the DDR is already
Hi Santiago,
On 1/29/19 5:12 AM, Santiago Piccinini wrote:
> Datasheet states that both PCI ranges are of 0x200 size:
> 0x1000_-0x11FF_FFF and 0x1200_-0x13FF_.
>
> Signed-off-by: Santiago Piccinini
Each PCIe root complex region is 32MB wide indeed.
> ---
>
Hi,
thank you for fixing this, the patch looks good to me.
On Tue, Jan 29, 2019 at 04:20:56AM +, Santiago Piccinini via openwrt-devel
wrote:
> The sender domain has a DMARC Reject/Quarantine policy which disallows
> sending mailing list messages using the original "From" header.
>
> To
The sender domain has a DMARC Reject/Quarantine policy which disallows
sending mailing list messages using the original "From" header.
To mitigate this problem, the original message has been wrapped
automatically by the mailing list software.--- Begin Message ---
Datasheet states that both PCI
