Dear Mingyu,
It works perfectly after adding the second spi clock:
https://gist.github.com/Noltari/9231b6c73c3b36e681ef
I'm sorry but I couldn't test this before.
Regards,
Álvaro.
El 23/11/2015 a las 2:41, Mingyu Li escribió:
Dear Sir.
you need to modify kernel file at "arch/mips/ralink/rt30
Hi,
why did you not send a patch for that ? please send it ASAP !
John
On 23/11/2015 02:41, Mingyu Li wrote:
> Dear Sir.
>
> you need to modify kernel file at "arch/mips/ralink/rt305x.c"
> add the code below.
>
> ralink_clk_add("1b00.spi", sys_rate);
> +ralink_clk_a
Dear Sir.
you need to modify kernel file at "arch/mips/ralink/rt305x.c"
add the code below.
ralink_clk_add("1b00.spi", sys_rate);
+ralink_clk_add("1b40.spi", sys_rate);
ralink_clk_add("1100.timer", wdt_rate);
please let me know if the second spi works. if work
On 22/11/2015 16:15, Álvaro Fernández Rojas wrote:
> Hello guys,
>
> I've just tested this patch on my VoCore after it was applied on r47580.
> I had to make the following changes:
> https://github.com/openwrt-es/openwrt/commit/e040cf00441e973978a6c168b346b13e33f37853
>
>
> However, I'm gettin
Hello guys,
I've just tested this patch on my VoCore after it was applied on r47580.
I had to make the following changes:
https://github.com/openwrt-es/openwrt/commit/e040cf00441e973978a6c168b346b13e33f37853
However, I'm getting the following error: "spi-rt2880 1b40.spi:
unable to get SYS c
Signed-off-by: Michael Lee
---
target/linux/ramips/dts/mt7620a.dtsi | 32 +-
target/linux/ramips/dts/mt7620n.dtsi | 32 +-
target/linux/ramips/dts/rt3050.dtsi| 6 +-
target/linux/ramips/dts/rt3352.dtsi| 31 +-
target/linux/ramips/dt
