Commit 0959f20863b119c5ca7d1e663bc22e6329814386 introduced new x64 functions
for saving and restoring the FPU control registers. The patch was correct,
but used a very misleading variable name "addr", while in fact these functions
pass values - the actual bit mask saved in those register - not addresses.
This patch only changes variable names - it should have no functional
significance.
Signed-off-by: Nadav Har'El <n...@scylladb.com>
---
arch/x64/processor.hh | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/x64/processor.hh b/arch/x64/processor.hh
index 250153be..6b1fbf66 100644
--- a/arch/x64/processor.hh
+++ b/arch/x64/processor.hh
@@ -413,26 +413,26 @@ inline bool rdrand(u64* dest)
inline uint32_t stmxcsr()
{
- uint32_t addr;
- asm volatile ("stmxcsr %0" : "=m" (addr));
- return addr;
+ uint32_t bits;
+ asm volatile ("stmxcsr %0" : "=m" (bits));
+ return bits;
}
-inline void ldmxcsr(uint32_t addr)
+inline void ldmxcsr(uint32_t bits)
{
- asm volatile ("ldmxcsr %0" : : "m" (addr));
+ asm volatile ("ldmxcsr %0" : : "m" (bits));
}
inline uint16_t fnstcw()
{
- uint16_t addr;
- asm volatile ("fnstcw %0" : "=m" (addr));
- return addr;
+ uint16_t bits;
+ asm volatile ("fnstcw %0" : "=m" (bits));
+ return bits;
}
-inline void fldcw(uint16_t addr)
+inline void fldcw(uint16_t bits)
{
- asm volatile ("fldcw %0" : : "m" (addr));
+ asm volatile ("fldcw %0" : : "m" (bits));
}
struct task_state_segment {
--
2.14.3
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