On Thu, Feb 03, 2005 at 06:26:16AM -0800, Simon Riggs wrote:
> > From: Tom Lane [mailto:[EMAIL PROTECTED] wrote
> > "Simon Riggs" <[EMAIL PROTECTED]> writes:
> > > It looks like padding out LWLock struct would ensure that
> > each of those
> > > were in separate cache lines?
> >
> > I've looked at
> From: Tom Lane [mailto:[EMAIL PROTECTED] wrote
> "Simon Riggs" <[EMAIL PROTECTED]> writes:
> >> From: Tom Lane [mailto:[EMAIL PROTECTED] wrote
> >> I've looked at this before and I think it's a nonstarter;
> >> increasing the
> >> size of a spinlock to 128 bytes is just not reasonable.
>
> > Well
"Simon Riggs" <[EMAIL PROTECTED]> writes:
>> From: Tom Lane [mailto:[EMAIL PROTECTED] wrote
>> I've looked at this before and I think it's a nonstarter;
>> increasing the
>> size of a spinlock to 128 bytes is just not reasonable.
> Well, the performance is unreasonably poor, so its time to do some
> From: Tom Lane [mailto:[EMAIL PROTECTED] wrote
> "Simon Riggs" <[EMAIL PROTECTED]> writes:
> > It looks like padding out LWLock struct would ensure that
> each of those
> > were in separate cache lines?
>
> I've looked at this before and I think it's a nonstarter;
> increasing the
> size of a spi
Simon Riggs wrote:
...and BTW, what is MMCacheLock?? is that an attempt at padding already?
One would hope not, as it would be a totally braindead attempt :) It
appears to have been formerly used by smgr/mm.c; when that was removed,
the MMCacheLock should have been removed but was not. Barring an
"Simon Riggs" <[EMAIL PROTECTED]> writes:
> It looks like padding out LWLock struct would ensure that each of those
> were in separate cache lines?
I've looked at this before and I think it's a nonstarter; increasing the
size of a spinlock to 128 bytes is just not reasonable. (Remember there
are
Following some advice from Intel,
http://www.intel.com/cd/ids/developer/asmo-na/eng/technologies/threading
/20469.htm?page=2
I'm looking at whether the LWLock data structures may be within the same
cache line.
Intel uses 128 byte cache lines on its high end processors.
slru.c uses BUFFERALIGN wh
