Author: sparky Date: Sun Nov 19 06:01:21 2006 GMT Module: SOURCES Tag: HEAD ---- Log message: - linux-2.6-sk98lin-8.36.1.3.patch
---- Files affected: SOURCES: kernel-desktop-sk98lin.patch (1.1 -> 1.2) ---- Diffs: ================================================================ Index: SOURCES/kernel-desktop-sk98lin.patch diff -u SOURCES/kernel-desktop-sk98lin.patch:1.1 SOURCES/kernel-desktop-sk98lin.patch:1.2 --- SOURCES/kernel-desktop-sk98lin.patch:1.1 Mon Jun 19 14:52:46 2006 +++ SOURCES/kernel-desktop-sk98lin.patch Sun Nov 19 07:01:15 2006 @@ -1,6 +1,6 @@ diff -ruN linux/drivers/net/sk98lin/Makefile linux-new/drivers/net/sk98lin/Makefile ---- linux/drivers/net/sk98lin/Makefile 2006-06-18 01:49:35.000000000 +0000 -+++ linux-new/drivers/net/sk98lin/Makefile 2006-06-19 12:44:12.000000000 +0000 +--- linux/drivers/net/sk98lin/Makefile 2006-09-20 05:42:06.000000000 +0200 ++++ linux-new/drivers/net/sk98lin/Makefile 2006-09-20 18:58:01.423265750 +0200 @@ -1,6 +1,59 @@ +#****************************************************************************** # @@ -40,9 +40,8 @@ +# History: +# +# $Log$ -+# Revision 1.1 2006/06/19 12:52:46 sparky -+# - http://www.skd.de/e_en/products/adapters/pci_64/sk-98xx_v20/software/linux/driver/install-8_32.tar.bz2 -+# version 8.32.2.3 ++# Revision 1.2 2006/11/19 06:01:15 sparky ++# - linux-2.6-sk98lin-8.36.1.3.patch +# +# Revision 1.9.2.1 2005/04/11 09:01:18 mlindner +# Fix: Copyright year changed @@ -111,8 +110,8 @@ - - diff -ruN linux/drivers/net/sk98lin/h/lm80.h linux-new/drivers/net/sk98lin/h/lm80.h ---- linux/drivers/net/sk98lin/h/lm80.h 2006-06-18 01:49:35.000000000 +0000 -+++ linux-new/drivers/net/sk98lin/h/lm80.h 2006-04-27 09:43:44.000000000 +0000 +--- linux/drivers/net/sk98lin/h/lm80.h 2006-09-20 05:42:06.000000000 +0200 ++++ linux-new/drivers/net/sk98lin/h/lm80.h 2006-07-28 14:13:54.000000000 +0200 @@ -2,8 +2,8 @@ * * Name: lm80.h @@ -141,8 +140,8 @@ ******************************************************************************/ diff -ruN linux/drivers/net/sk98lin/h/skaddr.h linux-new/drivers/net/sk98lin/h/skaddr.h ---- linux/drivers/net/sk98lin/h/skaddr.h 2006-06-18 01:49:35.000000000 +0000 -+++ linux-new/drivers/net/sk98lin/h/skaddr.h 2006-04-27 09:43:44.000000000 +0000 +--- linux/drivers/net/sk98lin/h/skaddr.h 2006-09-20 05:42:06.000000000 +0200 ++++ linux-new/drivers/net/sk98lin/h/skaddr.h 2006-07-28 14:13:54.000000000 +0200 @@ -2,14 +2,15 @@ * * Name: skaddr.h @@ -250,8 +249,8 @@ extern int SkAddrSwap( SK_AC *pAC, diff -ruN linux/drivers/net/sk98lin/h/skcsum.h linux-new/drivers/net/sk98lin/h/skcsum.h ---- linux/drivers/net/sk98lin/h/skcsum.h 2006-06-18 01:49:35.000000000 +0000 -+++ linux-new/drivers/net/sk98lin/h/skcsum.h 2006-04-27 09:43:44.000000000 +0000 +--- linux/drivers/net/sk98lin/h/skcsum.h 2006-09-20 05:42:06.000000000 +0200 ++++ linux-new/drivers/net/sk98lin/h/skcsum.h 2006-07-28 14:13:54.000000000 +0200 @@ -2,14 +2,15 @@ * * Name: skcsum.h @@ -302,8 +301,8 @@ SK_AC *pAc, unsigned ReceiveFlags, diff -ruN linux/drivers/net/sk98lin/h/skdebug.h linux-new/drivers/net/sk98lin/h/skdebug.h ---- linux/drivers/net/sk98lin/h/skdebug.h 2006-06-18 01:49:35.000000000 +0000 -+++ linux-new/drivers/net/sk98lin/h/skdebug.h 2006-04-27 09:43:44.000000000 +0000 +--- linux/drivers/net/sk98lin/h/skdebug.h 2006-09-20 05:42:06.000000000 +0200 ++++ linux-new/drivers/net/sk98lin/h/skdebug.h 2006-07-28 14:13:54.000000000 +0200 @@ -2,23 +2,24 @@ * * Name: skdebug.h @@ -361,8 +360,8 @@ /* Debug events */ diff -ruN linux/drivers/net/sk98lin/h/skdrv1st.h linux-new/drivers/net/sk98lin/h/skdrv1st.h ---- linux/drivers/net/sk98lin/h/skdrv1st.h 2006-06-18 01:49:35.000000000 +0000 -+++ linux-new/drivers/net/sk98lin/h/skdrv1st.h 2006-04-27 09:43:45.000000000 +0000 +--- linux/drivers/net/sk98lin/h/skdrv1st.h 2006-09-20 05:42:06.000000000 +0200 ++++ linux-new/drivers/net/sk98lin/h/skdrv1st.h 2006-07-28 14:13:56.000000000 +0200 @@ -2,8 +2,8 @@ * * Name: skdrv1st.h @@ -480,8 +479,8 @@ + * + ******************************************************************************/ diff -ruN linux/drivers/net/sk98lin/h/skdrv2nd.h linux-new/drivers/net/sk98lin/h/skdrv2nd.h ---- linux/drivers/net/sk98lin/h/skdrv2nd.h 2006-06-18 01:49:35.000000000 +0000 -+++ linux-new/drivers/net/sk98lin/h/skdrv2nd.h 2006-04-27 09:43:45.000000000 +0000 +--- linux/drivers/net/sk98lin/h/skdrv2nd.h 2006-09-20 05:42:06.000000000 +0200 ++++ linux-new/drivers/net/sk98lin/h/skdrv2nd.h 2006-07-28 14:13:56.000000000 +0200 @@ -1,17 +1,17 @@ /****************************************************************************** * @@ -1609,8 +1608,8 @@ + * + ******************************************************************************/ diff -ruN linux/drivers/net/sk98lin/h/skerror.h linux-new/drivers/net/sk98lin/h/skerror.h ---- linux/drivers/net/sk98lin/h/skerror.h 2006-06-18 01:49:35.000000000 +0000 -+++ linux-new/drivers/net/sk98lin/h/skerror.h 2006-04-27 09:43:44.000000000 +0000 +--- linux/drivers/net/sk98lin/h/skerror.h 2006-09-20 05:42:06.000000000 +0200 ++++ linux-new/drivers/net/sk98lin/h/skerror.h 2006-07-28 14:13:54.000000000 +0200 @@ -2,23 +2,24 @@ * * Name: skerror.h @@ -1660,8 +1659,8 @@ #endif /* _INC_SKERROR_H_ */ + diff -ruN linux/drivers/net/sk98lin/h/skgedrv.h linux-new/drivers/net/sk98lin/h/skgedrv.h ---- linux/drivers/net/sk98lin/h/skgedrv.h 2006-06-18 01:49:35.000000000 +0000 -+++ linux-new/drivers/net/sk98lin/h/skgedrv.h 2006-04-27 09:43:44.000000000 +0000 +--- linux/drivers/net/sk98lin/h/skgedrv.h 2006-09-20 05:42:06.000000000 +0200 ++++ linux-new/drivers/net/sk98lin/h/skgedrv.h 2006-07-28 14:13:54.000000000 +0200 @@ -2,23 +2,24 @@ * * Name: skgedrv.h @@ -1714,8 +1713,8 @@ +#define SK_DRV_PEX_LINK_WIDTH 17 /* PEX negotiated Link width not maximum */ #endif /* __INC_SKGEDRV_H_ */ diff -ruN linux/drivers/net/sk98lin/h/skgehw.h linux-new/drivers/net/sk98lin/h/skgehw.h ---- linux/drivers/net/sk98lin/h/skgehw.h 2006-06-18 01:49:35.000000000 +0000 -+++ linux-new/drivers/net/sk98lin/h/skgehw.h 2006-04-27 09:43:44.000000000 +0000 +--- linux/drivers/net/sk98lin/h/skgehw.h 2006-09-20 05:42:06.000000000 +0200 ++++ linux-new/drivers/net/sk98lin/h/skgehw.h 2006-07-28 14:13:54.000000000 +0200 @@ -2,23 +2,24 @@ * * Name: skgehw.h @@ -2762,7 +2761,7 @@ /* B2_CONN_TYP 8 bit Connector type */ /* B2_PMD_TYP 8 bit PMD type */ /* Values of connector and PMD type comply to SysKonnect internal std */ -@@ -908,19 +1391,75 @@ +@@ -908,19 +1391,78 @@ #define CFG_CHIP_R_MSK (0xf<<4) /* Bit 7.. 4: Chip Revision */ /* Bit 3.. 2: reserved */ #define CFG_DIS_M2_CLK BIT_1S /* Disable Clock for 2nd MAC */ @@ -2795,6 +2794,9 @@ +#define CHIP_REV_YU_EC_U_A0 1 /* Chip Rev. for Yukon-EC Ultra A0 */ +#define CHIP_REV_YU_EC_U_A1 2 /* Chip Rev. for Yukon-EC Ultra A1 */ + ++#define CHIP_REV_YU_FE_A1 1 /* Chip Rev. for Yukon-FE A1 */ ++#define CHIP_REV_YU_FE_A2 3 /* Chip Rev. for Yukon-FE A2 */ ++ +/* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */ +#define Y2_STATUS_LNK2_INAC BIT_7S /* Status Link 2 inactiv (0 = activ) */ +#define Y2_CLK_GAT_LNK2_DIS BIT_6S /* Disable PHY clock for Link 2 */ @@ -2841,7 +2843,7 @@ /* B2_LD_CTRL 8 bit EPROM loader control register */ /* Bits are currently reserved */ -@@ -960,9 +1499,6 @@ +@@ -960,9 +1502,6 @@ #define DPT_START BIT_1S /* Start Descriptor Poll Timer */ #define DPT_STOP BIT_0S /* Stop Descriptor Poll Timer */ @@ -2851,7 +2853,7 @@ /* B2_TST_CTRL1 8 bit Test Control Register 1 */ #define TST_FRC_DPERR_MR BIT_7S /* force DATAPERR on MST RD */ #define TST_FRC_DPERR_MW BIT_6S /* force DATAPERR on MST WR */ -@@ -975,14 +1511,14 @@ +@@ -975,14 +1514,14 @@ /* B2_TST_CTRL2 8 bit Test Control Register 2 */ /* Bit 7.. 4: reserved */ @@ -2868,7 +2870,7 @@ #define GP_DIR_9 BIT_25 /* IO_9 direct, 0=In/1=Out */ #define GP_DIR_8 BIT_24 /* IO_8 direct, 0=In/1=Out */ #define GP_DIR_7 BIT_23 /* IO_7 direct, 0=In/1=Out */ -@@ -1009,15 +1545,15 @@ +@@ -1009,15 +1548,15 @@ #define I2C_FLAG BIT_31 /* Start read/write if WR */ #define I2C_ADDR (0x7fffL<<16) /* Bit 30..16: Addr to be RD/WR */ #define I2C_DEV_SEL (0x7fL<<9) /* Bit 15.. 9: I2C Device Select */ @@ -2892,7 +2894,7 @@ #define I2C_16K_DEV (6<<1) /* 6: 16384 Bytes */ #define I2C_32K_DEV (7<<1) /* 7: 32768 Bytes */ #define I2C_STOP BIT_0 /* Interrupt I2C transfer */ -@@ -1026,16 +1562,14 @@ +@@ -1026,16 +1565,14 @@ /* Bit 31.. 1 reserved */ #define I2C_CLR_IRQ BIT_0 /* Clear I2C IRQ */ @@ -2914,7 +2916,7 @@ /* B2_BSC_CTRL 8 bit Blink Source Counter Control */ -@@ -1052,16 +1586,20 @@ +@@ -1052,16 +1589,20 @@ #define BSC_T_OFF BIT_1S /* Test mode off */ #define BSC_T_STEP BIT_0S /* Test step */ @@ -2938,7 +2940,7 @@ /* Bit 7.. 2: reserved */ #define RI_RST_CLR BIT_1S /* Clear RAM Interface Reset */ #define RI_RST_SET BIT_0S /* Set RAM Interface Reset */ -@@ -1171,7 +1709,7 @@ +@@ -1171,7 +1712,7 @@ /* Bit 31..16: reserved */ #define BC_MAX 0xffff /* Bit 15.. 0: Byte counter */ @@ -2947,7 +2949,7 @@ /* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */ /* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */ /* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */ -@@ -1212,13 +1750,48 @@ +@@ -1212,13 +1753,48 @@ CSR_SV_RUN | CSR_DREAD_RUN | CSR_DWRITE_RUN |\ CSR_TRANS_RUN) @@ -2997,7 +2999,7 @@ #define F_FIFO_LEVEL (0x1fL<<16) /* Bit 23..16: # of Qwords in FIFO */ /* Bit 15..11: reserved */ #define F_WATER_MARK 0x0007ffL /* Bit 10.. 0: Watermark */ -@@ -1260,6 +1833,13 @@ +@@ -1260,6 +1836,13 @@ /* Bit 3: reserved */ #define T3_VRAM_MSK 7 /* Bit 2.. 0: Virtual RAM Buffer Address */ @@ -3011,7 +3013,7 @@ /* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */ /* RB_START 32 bit RAM Buffer Start Address */ /* RB_END 32 bit RAM Buffer End Address */ -@@ -1275,24 +1855,24 @@ +@@ -1275,24 +1858,24 @@ #define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */ /* RB_TST2 8 bit RAM Buffer Test Register 2 */ @@ -3043,7 +3045,7 @@ #define RB_ENA_STFWD BIT_5S /* Enable Store & Forward */ #define RB_DIS_STFWD BIT_4S /* Disable Store & Forward */ #define RB_ENA_OP_MD BIT_3S /* Enable Operation Mode */ -@@ -1300,16 +1880,31 @@ +@@ -1300,16 +1883,31 @@ #define RB_RST_CLR BIT_1S /* Clear RAM Buf STM Reset */ #define RB_RST_SET BIT_0S /* Set RAM Buf STM Reset */ @@ -3077,7 +3079,7 @@ /* TX_MFF_WSP 32 bit Transmit MAC FIFO WR Shadow Pointer */ /* TX_MFF_RP 32 bit Transmit MAC FIFO Read Pointer */ /* TX_MFF_PC 32 bit Transmit MAC FIFO Packet Cnt */ -@@ -1359,9 +1954,9 @@ +@@ -1359,9 +1957,9 @@ /* RX_MFF_TST2 8 bit Receive MAC FIFO Test Register 2 */ /* TX_MFF_TST2 8 bit Transmit MAC FIFO Test Register 2 */ /* Bit 7: reserved */ @@ -3090,7 +3092,7 @@ #define MFF_PC_DEC BIT_3S /* Packet Counter Decrement */ #define MFF_PC_T_ON BIT_2S /* Packet Counter Test On */ #define MFF_PC_T_OFF BIT_1S /* Packet Counter Test Off */ -@@ -1372,7 +1967,7 @@ +@@ -1372,7 +1970,7 @@ /* Bit 7: reserved */ #define MFF_WP_T_ON BIT_6S /* Write Pointer Test On */ #define MFF_WP_T_OFF BIT_5S /* Write Pointer Test Off */ @@ -3099,7 +3101,7 @@ /* Bit 3: reserved */ #define MFF_RP_T_ON BIT_2S /* Read Pointer Test On */ #define MFF_RP_T_OFF BIT_1S /* Read Pointer Test Off */ -@@ -1391,12 +1986,16 @@ +@@ -1391,12 +1989,16 @@ /* RX_LED_CTRL 8 bit Receive LED Cnt Control Reg */ /* TX_LED_CTRL 8 bit Transmit LED Cnt Control Reg */ @@ -3120,7 +3122,7 @@ /* RX_LED_TST 8 bit Receive LED Cnt Test Register */ /* TX_LED_TST 8 bit Transmit LED Cnt Test Register */ -@@ -1407,86 +2006,142 @@ +@@ -1407,86 +2009,142 @@ #define LED_T_STEP BIT_0S /* LED Counter Step */ /* LNK_LED_REG 8 bit Link LED Register */ @@ -3315,7 +3317,7 @@ #define GPC_75_OHM BIT_26 /* Use 75 Ohm Termination instead of 50 */ #define GPC_DIS_FC BIT_25 /* Disable Automatic Fiber/Copper Detection */ #define GPC_DIS_SLEEP BIT_24 /* Disable Energy Detect */ -@@ -1501,15 +2156,24 @@ +@@ -1501,15 +2159,24 @@ #define GPC_ANEG_2 BIT_15 /* ANEG[2] */ #define GPC_ANEG_1 BIT_14 /* ANEG[1] */ #define GPC_ENA_PAUSE BIT_13 /* Enable Pause (SYM_OR_REM) */ @@ -3345,7 +3347,7 @@ #define GPC_HWCFG_GMII_COP (GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | \ GPC_HWCFG_M_1 | GPC_HWCFG_M_0) -@@ -1540,20 +2204,20 @@ +@@ -1540,20 +2207,20 @@ /* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */ /* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */ @@ -3376,7 +3378,7 @@ /* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */ -@@ -1579,15 +2243,19 @@ +@@ -1579,15 +2246,19 @@ #define WOL_CTL_DEFAULT \ (WOL_CTL_DIS_PME_ON_LINK_CHG | \ @@ -3401,7 +3403,7 @@ #define SK_NUM_WOL_PATTERN 7 #define SK_PATTERN_PER_WORD 4 #define SK_BITMASK_PATTERN 7 -@@ -1597,26 +2265,28 @@ +@@ -1597,26 +2268,28 @@ #define WOL_LENGTH_SHIFT 8 @@ -3435,7 +3437,7 @@ SK_U32 TxRes2; /* 32 bit reserved field */ } SK_HWTXD; -@@ -1624,33 +2294,266 @@ +@@ -1624,33 +2297,266 @@ typedef struct s_HwRxd { SK_U32 volatile RxCtrl; /* Receive Buffer Control Field */ SK_U32 RxNext; /* Physical Address Pointer to the next RxD */ @@ -3715,7 +3717,7 @@ /* Descriptor Bit Definition */ /* TxCtrl Transmit Buffer Control Field */ -@@ -1685,6 +2588,10 @@ +@@ -1685,6 +2591,10 @@ /* macros ********************************************************************/ @@ -3726,7 +3728,7 @@ /* Receive and Transmit Queues */ #define Q_R1 0x0000 /* Receive Queue 1 */ #define Q_R2 0x0080 /* Receive Queue 2 */ -@@ -1693,6 +2600,10 @@ +@@ -1693,6 +2603,10 @@ #define Q_XS2 0x0300 /* Synchronous Transmit Queue 2 */ #define Q_XA2 0x0380 /* Asynchronous Transmit Queue 2 */ @@ -3737,7 +3739,7 @@ /* * Macro Q_ADDR() * -@@ -1704,11 +2615,27 @@ +@@ -1704,11 +2618,27 @@ * Offs Queue register offset. * Values: Q_D, Q_DA_L ... Q_T2, Q_T3 * @@ -3766,7 +3768,7 @@ * Macro RB_ADDR() * * Use this macro to access the RAM Buffer Registers. -@@ -1719,14 +2646,14 @@ +@@ -1719,14 +2649,14 @@ * Offs Queue register offset. * Values: RB_START, RB_END ... RB_LEV, RB_CTRL * @@ -3784,7 +3786,7 @@ /* * Macro MR_ADDR() -@@ -1740,19 +2667,10 @@ +@@ -1740,19 +2670,10 @@ * Values: RX_MFF_EA, RX_MFF_WP ... LNK_LED_REG, * TX_MFF_EA, TX_MFF_WP ... TX_LED_TST * @@ -3805,7 +3807,7 @@ /* * macros to access the XMAC (GENESIS only) * -@@ -1777,22 +2695,31 @@ +@@ -1777,22 +2698,31 @@ #define XMA(Mac, Reg) \ ((BASE_XMAC_1 + (Mac) * (BASE_XMAC_2 - BASE_XMAC_1)) | ((Reg) << 1)) @@ -3848,7 +3850,7 @@ } /* Remember: we are always writing to / reading from LITTLE ENDIAN memory */ -@@ -1802,13 +2729,13 @@ +@@ -1802,13 +2732,13 @@ SK_U8 *pByte; \ pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \ SK_IN16((IoC), XMA((Mac), (Reg)), &Word); \ @@ -3867,7 +3869,7 @@ pByte[5] = (SK_U8)((Word >> 8) & 0x00ff); \ } -@@ -1818,10 +2745,10 @@ +@@ -1818,10 +2748,10 @@ SK_OUT16((IoC), XMA((Mac), (Reg)), (SK_U16) \ (((SK_U16)(pByte[0]) & 0x00ff) | \ (((SK_U16)(pByte[1]) << 8) & 0xff00))); \ @@ -3880,7 +3882,7 @@ (((SK_U16)(pByte[4]) & 0x00ff) | \ (((SK_U16)(pByte[5]) << 8) & 0xff00))); \ } -@@ -1831,16 +2758,16 @@ +@@ -1831,16 +2761,16 @@ SK_U8 SK_FAR *pByte; \ pByte = (SK_U8 SK_FAR *)&((SK_U8 SK_FAR *)(pVal))[0]; \ SK_IN16((IoC), XMA((Mac), (Reg)), &Word); \ @@ -3904,7 +3906,7 @@ pByte[7] = (SK_U8)((Word >> 8) & 0x00ff); \ } -@@ -1850,13 +2777,13 @@ +@@ -1850,13 +2780,13 @@ SK_OUT16((IoC), XMA((Mac), (Reg)), (SK_U16) \ (((SK_U16)(pByte[0]) & 0x00ff)| \ (((SK_U16)(pByte[1]) << 8) & 0xff00))); \ @@ -3921,7 +3923,7 @@ (((SK_U16)(pByte[6]) & 0x00ff)| \ (((SK_U16)(pByte[7]) << 8) & 0xff00))); \ } -@@ -1866,12 +2793,12 @@ +@@ -1866,12 +2796,12 @@ * * GM_IN16(), to read a 16 bit register (e.g. GM_GP_STAT) * GM_OUT16(), to write a 16 bit register (e.g. GM_GP_CTRL) @@ -3938,7 +3940,7 @@ * * para: * Mac GMAC to access values: MAC_1 or MAC_2 -@@ -1885,22 +2812,31 @@ +@@ -1885,22 +2815,31 @@ #define GMA(Mac, Reg) \ ((BASE_GMAC_1 + (Mac) * (BASE_GMAC_2 - BASE_GMAC_1)) | (Reg)) @@ -3981,7 +3983,7 @@ } #define GM_INADDR(IoC, Mac, Reg, pVal) { \ -@@ -1908,13 +2844,13 @@ +@@ -1908,13 +2847,13 @@ SK_U8 *pByte; \ pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \ SK_IN16((IoC), GMA((Mac), (Reg)), &Word); \ @@ -4000,7 +4002,7 @@ pByte[5] = (SK_U8)((Word >> 8) & 0x00ff); \ } -@@ -1924,10 +2860,10 @@ +@@ -1924,10 +2863,10 @@ SK_OUT16((IoC), GMA((Mac), (Reg)), (SK_U16) \ (((SK_U16)(pByte[0]) & 0x00ff) | \ (((SK_U16)(pByte[1]) << 8) & 0xff00))); \ @@ -4013,7 +4015,7 @@ (((SK_U16)(pByte[4]) & 0x00ff) | \ (((SK_U16)(pByte[5]) << 8) & 0xff00))); \ } -@@ -1937,16 +2873,16 @@ +@@ -1937,16 +2876,16 @@ SK_U8 *pByte; \ pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \ SK_IN16((IoC), GMA((Mac), (Reg)), &Word); \ @@ -4037,7 +4039,7 @@ pByte[7] = (SK_U8)((Word >> 8) & 0x00ff); \ } -@@ -1956,13 +2892,13 @@ +@@ -1956,13 +2895,13 @@ SK_OUT16((IoC), GMA((Mac), (Reg)), (SK_U16) \ (((SK_U16)(pByte[0]) & 0x00ff)| \ (((SK_U16)(pByte[1]) << 8) & 0xff00))); \ @@ -4054,7 +4056,7 @@ (((SK_U16)(pByte[6]) & 0x00ff)| \ (((SK_U16)(pByte[7]) << 8) & 0xff00))); \ } -@@ -1980,8 +2916,8 @@ +@@ -1980,8 +2919,8 @@ #define SK_PHY_BCOM 1 /* Broadcom BCM5400 */ #define SK_PHY_LONE 2 /* Level One LXT1000 */ #define SK_PHY_NAT 3 /* National DP83891 */ @@ -4065,7 +4067,7 @@ /* * PHY addresses (bits 12..8 of PHY address reg) -@@ -2010,30 +2946,30 @@ +@@ -2010,30 +2949,30 @@ * * usage: PHY_READ(IoC, pPort, MAC_1, PHY_CTRL, Value); * Warning: a PHY_READ on an uninitialized PHY (PHY still in reset) never @@ -4102,7 +4104,7 @@ XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \ __i++; \ if (__i > 100000) { \ -@@ -2044,7 +2980,7 @@ +@@ -2044,7 +2983,7 @@ } \ } while ((Mmu & XM_MMU_PHY_RDY) == 0); \ XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \ @@ -4111,7 +4113,7 @@ } #endif /* DEBUG */ -@@ -2052,17 +2988,17 @@ +@@ -2052,17 +2991,17 @@ SK_U16 Mmu; \ \ if ((pPort)->PhyType != SK_PHY_XMAC) { \ @@ -4133,7 +4135,7 @@ } /* -@@ -2071,12 +3007,14 @@ +@@ -2071,12 +3010,14 @@ * Use this macro to access PCI config register from the I/O space. * * para: @@ -4150,7 +4152,7 @@ /* * Macro SK_HW_ADDR(Base, Addr) -@@ -2088,7 +3026,7 @@ +@@ -2088,7 +3029,7 @@ * Addr Address offset * * usage: May be used in SK_INxx and SK_OUTxx macros @@ -4159,7 +4161,7 @@ * *pVal = (SK_U8)inp(SK_HW_ADDR(pAC->Hw.Iop, Addr))) */ #ifdef SK_MEM_MAPPED_IO -@@ -2107,20 +3045,31 @@ +@@ -2107,20 +3048,31 @@ * para: * pAC Pointer to adapter context struct * IoC I/O context needed for SK I/O macros @@ -4196,9 +4198,9 @@ #endif /* __INC_SKGEHW_H */ + diff -ruN linux/drivers/net/sk98lin/h/skgehwt.h linux-new/drivers/net/sk98lin/h/skgehwt.h ---- linux/drivers/net/sk98lin/h/skgehwt.h 2006-06-18 01:49:35.000000000 +0000 -+++ linux-new/drivers/net/sk98lin/h/skgehwt.h 2006-04-27 09:43:44.000000000 +0000 -@@ -2,8 +2,8 @@ +--- linux/drivers/net/sk98lin/h/skgehwt.h 2006-09-20 05:42:06.000000000 +0200 ++++ linux-new/drivers/net/sk98lin/h/skgehwt.h 2006-07-28 14:13:54.000000000 +0200 +@@ -2,14 +2,15 @@ * * Name: skhwt.h * Project: Gigabit Ethernet Adapters, Event Scheduler Module @@ -4209,9 +4211,24 @@ * Purpose: Defines for the hardware timer functions * ******************************************************************************/ + + /****************************************************************************** + * ++ * LICENSE: + * (C)Copyright 1998-2002 SysKonnect GmbH. + * (C)Copyright 2002-2003 Marvell. + * +@@ -19,6 +20,7 @@ + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. ++ * /LICENSE + * + ******************************************************************************/ + diff -ruN linux/drivers/net/sk98lin/h/skgei2c.h linux-new/drivers/net/sk98lin/h/skgei2c.h ---- linux/drivers/net/sk98lin/h/skgei2c.h 2006-06-18 01:49:35.000000000 +0000 -+++ linux-new/drivers/net/sk98lin/h/skgei2c.h 1970-01-01 00:00:00.000000000 +0000 +--- linux/drivers/net/sk98lin/h/skgei2c.h 2006-09-20 05:42:06.000000000 +0200 ++++ linux-new/drivers/net/sk98lin/h/skgei2c.h 1970-01-01 01:00:00.000000000 +0100 @@ -1,210 +0,0 @@ -/****************************************************************************** - * @@ -4424,8 +4441,8 @@ -extern int SkLm80ReadSensor(SK_AC *pAC, SK_IOC IoC, SK_SENSOR *pSen); -#endif /* n_INC_SKGEI2C_H */ diff -ruN linux/drivers/net/sk98lin/h/skgeinit.h linux-new/drivers/net/sk98lin/h/skgeinit.h ---- linux/drivers/net/sk98lin/h/skgeinit.h 2006-06-18 01:49:35.000000000 +0000 -+++ linux-new/drivers/net/sk98lin/h/skgeinit.h 2006-04-27 09:43:44.000000000 +0000 +--- linux/drivers/net/sk98lin/h/skgeinit.h 2006-09-20 05:42:06.000000000 +0200 ++++ linux-new/drivers/net/sk98lin/h/skgeinit.h 2006-07-28 14:13:54.000000000 +0200 @@ -2,23 +2,24 @@ * * Name: skgeinit.h @@ -4684,7 +4701,7 @@ /* Link Partner Status */ #define SK_LIPA_UNKNOWN 0 /* Link partner is in unknown state */ -@@ -290,18 +307,174 @@ +@@ -290,18 +307,187 @@ /* Max. Auto-neg. timeouts before link detection in sense mode is reset */ #define SK_MAX_ANEG_TO 10 /* Max. 10 times the sense mode is reset */ @@ -4698,34 +4715,8 @@ +#define HWF_FORCE_AUTO_NEG 0x04000000UL /* Force Auto-Negotiation */ +#define HWF_CLK_GATING_ENABLE 0x02000000UL /* Enable Clock Gating */ +#define HWF_RED_CORE_CLK_SUP 0x01000000UL /* Reduced Core Clock supp. */ -+#define HWF_SYNC_TX_SUP 0x00800000UL /* Synch. Tx Queue available */ -+#define HWF_SINGLE_PORT_DEVICE 0x00400000UL /* Device has only one LAN IF */ -+#define HWF_JUMBO_FRAMES_SUP 0x00200000UL /* Jumbo Frames supported */ -+#define HWF_TX_TCP_CSUM_SUP 0x00100000UL /* TCP Tx checksum supported */ -+#define HWF_TX_UDP_CSUM_SUP 0x00080000UL /* UDP Tx checksum supported */ -+#define HWF_RX_CSUM_SUP 0x00040000UL /* RX checksum supported */ -+#define HWF_TCP_SEGM_SUP 0x00020000UL /* TCP segmentation supported */ -+#define HWF_RSS_HASH_SUP 0x00010000UL /* RSS Hash supported */ -+#define HWF_PORT_VLAN_SUP 0x00008000UL /* VLAN can be config per port*/ -+#define HWF_ROLE_PARAM_SUP 0x00004000UL /* Role parameter supported */ -+#define HWF_LOW_PMODE_SUP 0x00002000UL /* Low Power Mode supported */ <<Diff was trimmed, longer than 597 lines>> ---- CVS-web: http://cvs.pld-linux.org/SOURCES/kernel-desktop-sk98lin.patch?r1=1.1&r2=1.2&f=u _______________________________________________ pld-cvs-commit mailing list pld-cvs-commit@lists.pld-linux.org http://lists.pld-linux.org/mailman/listinfo/pld-cvs-commit
