Greetings,

The attached diff updates cad/opensta to a very recent commit.

This is a trivial update port-wise, but a big jump in terms of features/bug-fixing.


What's new upstream
===================
This is just an incomplete list of upstream's activity:
- set_power_activity -input applies to floating inputs;
- power reg activity revisited;
- Sta::insert_buffer;
- power use propagted activities for internal power;
- replace_cell checks;
- ConcreteCell/Port pointers to corresponding liberty;
- Liberty cell drive_resistance property;
- support equiv cells across libraries;
- set_clock_sense -> set_sense;
- get_lib_cells allow wildcard lib name;
- VerilogWriter now uses liberty bus port order;
- sdc matches for verilog port nets like \foo[2][0];
- write_verilog escaped bus names;
- create_clock redef preserve propagated;
- slew limits on ideal clk nets are not checked anymore;
- multi-driver net delay calc with multiple threads.


What's new in the port
======================
- updated maintainer email address;
- ApiChanges.txt added to ${PREFIX}/share/doc/opensta;
- I noticed that ChangeLog.txt is practically unmaintained, but since it is still part of the distribution files, I left it as it was; if it should be removed, just let me know; - there is now a regression suite (very basic, but still useful); I modified the Makefile to allow its execution; all tests are OK.

Tested on amd64 only.

--
Alessandro De Laurenzis
[mailto:jus...@atlantide.mooo.com]
Web: http://www.atlantide.mooo.com
LinkedIn: http://it.linkedin.com/in/delaurenzis
Index: Makefile
===================================================================
RCS file: /cvs/ports/cad/opensta/Makefile,v
retrieving revision 1.6
diff -u -p -u -p -r1.6 Makefile
--- Makefile    18 Dec 2019 07:42:27 -0000      1.6
+++ Makefile    8 Mar 2020 16:56:24 -0000
@@ -3,16 +3,15 @@
 COMMENT =      Parallax Static Timing Analyzer
 
 # use version number from git log
-DISTNAME =     opensta-2.0.12.20190329
-REVISION =     0
+DISTNAME =     opensta-2.0.18.20200308
 
 CATEGORIES =   cad
 
 GH_ACCOUNT =   abk-openroad
 GH_PROJECT =   OpenSTA
-GH_COMMIT =    ed3ad4fb3012feb53328a80df6ad01efd477f891
+GH_COMMIT =    d615f62fe412b0f12166e6d5559eacec43713e02
 
-MAINTAINER =   Alessandro De Laurenzis <jus...@atlantide.t28.net>
+MAINTAINER =   Alessandro De Laurenzis <jus...@atlantide.mooo.com>
 
 # GPLv3
 PERMIT_PACKAGE =       Yes
@@ -37,15 +36,18 @@ BUILD_DEPENDS =     devel/bison \
 CONFIGURE_ARGS = -DTCL_HEADER=${MODTCL_INCDIR}/tcl.h \
                 -DCUDD=${LOCALBASE}
 
-NO_TEST =      Yes
-
 pre-configure:
        cd ${WRKSRC}/etc && ${MODTCL_TCLSH_ADJ} TclEncode.tcl SwigCleanup.tcl
+       cd ${WRKSRC}/test && ${MODTCL_TCLSH_ADJ} regression
 
 post-install:
        ${INSTALL_DATA_DIR} ${PREFIX}/share/doc/opensta
        ${INSTALL_DATA} ${WRKSRC}/doc/OpenSTA.pdf ${PREFIX}/share/doc/opensta
        ${INSTALL_DATA} ${WRKSRC}/doc/ChangeLog.txt ${PREFIX}/share/doc/opensta
        ${INSTALL_DATA} ${WRKSRC}/doc/StaApi.txt ${PREFIX}/share/doc/opensta
+       ${INSTALL_DATA} ${WRKSRC}/doc/ApiChanges.txt ${PREFIX}/share/doc/opensta
+
+do-test:
+       cd ${WRKDIST} && test/regression all
 
 .include <bsd.port.mk>
Index: distinfo
===================================================================
RCS file: /cvs/ports/cad/opensta/distinfo,v
retrieving revision 1.2
diff -u -p -u -p -r1.2 distinfo
--- distinfo    30 Mar 2019 11:50:06 -0000      1.2
+++ distinfo    8 Mar 2020 16:56:24 -0000
@@ -1,2 +1,2 @@
-SHA256 (opensta-2.0.12.20190329-ed3ad4fb.tar.gz) = 
fRJ9YJuTPng7bgIxD1aODNL63xOiR9FIbmI4PMcdi8w=
-SIZE (opensta-2.0.12.20190329-ed3ad4fb.tar.gz) = 911049
+SHA256 (opensta-2.0.18.20200308-d615f62f.tar.gz) = 
+039qKdPjmM4LqUv5qbo9L3akiS9f98gzulJgXyNJT4=
+SIZE (opensta-2.0.18.20200308-d615f62f.tar.gz) = 4859083
Index: pkg/PLIST
===================================================================
RCS file: /cvs/ports/cad/opensta/pkg/PLIST,v
retrieving revision 1.2
diff -u -p -u -p -r1.2 PLIST
--- pkg/PLIST   30 Mar 2019 11:50:06 -0000      1.2
+++ pkg/PLIST   8 Mar 2020 16:56:24 -0000
@@ -35,6 +35,7 @@ include/DelayNormal2.hh
 include/DeratingFactors.hh
 include/DisabledPorts.hh
 include/DisallowCopyAssign.hh
+include/DispatchQueue.hh
 include/DmpCeff.hh
 include/DmpDelayCalc.hh
 include/EnumNameMap.hh
@@ -64,6 +65,7 @@ include/Levelize.hh
 include/Liberty.hh
 include/LibertyBuilder.hh
 include/LibertyClass.hh
+include/LibertyExpr.hh
 include/LibertyParser.hh
 include/LibertyReader.hh
 include/LibertyReaderPvt.hh
@@ -81,7 +83,8 @@ include/Network.hh
 include/NetworkClass.hh
 include/NetworkCmp.hh
 include/NullParasitics.hh
-include/ObjectIndex.hh
+include/ObjectId.hh
+include/ObjectTable.hh
 include/Parasitics.hh
 include/ParasiticsClass.hh
 include/ParseBus.hh
@@ -97,7 +100,6 @@ include/PathVertex.hh
 include/PathVertexRep.hh
 include/PatternMatch.hh
 include/PinPair.hh
-include/Pool.hh
 include/PortDelay.hh
 include/PortDirection.hh
 include/PortExtCap.hh
@@ -139,7 +141,6 @@ include/StringUtil.hh
 include/TableModel.hh
 include/Tag.hh
 include/TagGroup.hh
-include/ThreadForEach.hh
 include/TimingArc.hh
 include/TimingModel.hh
 include/TimingRole.hh
@@ -150,9 +151,10 @@ include/Units.hh
 include/UnorderedMap.hh
 include/UnorderedSet.hh
 include/Vector.hh
-include/Verilog.hh
 include/VerilogNamespace.hh
 include/VerilogReader.hh
+include/VerilogReaderPvt.hh
+include/VerilogWriter.hh
 include/VertexVisitor.hh
 include/VisitPathEnds.hh
 include/VisitPathGroupVertices.hh
@@ -162,8 +164,9 @@ include/WritePathSpice.hh
 include/WriteSdc.hh
 include/WriteSdcPvt.hh
 include/Zlib.hh
-lib/libOpenSTA.a
+@static-lib lib/libOpenSTA.a
 share/doc/opensta/
+share/doc/opensta/ApiChanges.txt
 share/doc/opensta/ChangeLog.txt
 share/doc/opensta/OpenSTA.pdf
 share/doc/opensta/StaApi.txt

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