Bob,
Two points about this --
1) The list of footprints in the library symbol is merely possible
choices -- you don't have to use any one of these. So changing the
footprint list in the library should NOT update all the footprints for those
symbols in the schematic.
2) Use global edit if you real
> Sounds like way to much confusion to me.
I don't mean that you always have to use formulas. I wrote:
'What we need is the >>>option<<< of using formulas and expressions'
What I mean is that we can do the job in the usual way, but for the
exceptions and the specials it might be helpfull.
We
I wish all of the members of this list all the best wishes for Xmas
and the New Year. Thanks very much for the useful information
gathered during the year.
Brian
Brian Merskey
Institute for Maritime Technology
Phone: (2721)7861092
Fax: (2721)7862189
E-mail: [EMAIL PROTECTED]
* * * * * * *
Hello all,
We have been given responsibility for a large suite of technology from a
defunct US company (once owned by Cadence). The schematics are in OrCad
capture (DSN) format, but the PCBs are unknown. I thought either OrCad
Layout or Cadence Allegro but neither creates *.PCB files.
Inspe
I did this last year when I realized the limitations of Camtastic in merging
separate PCB's.
I had to have separate PCBs, since the front panel controls (switches, rotary
encoder, display) are all different stand off heights. I used the 1mm flex to
interconnect.
What I did was to segregate th
Hi,
I am wondering "Un-Connected Pin Constraint" how to use it.
I set all unconnected / no net pads to Pad Class, Members "box",
but all unconnected pad that I have in my desing are green, does this
Rule work opposite... This Rule checks all pads that are IN MEMBERS "box"
instead of NOT to check
Has anybody ever thought about having local meetings for Protel users? This
way we can put a "face" to the people in the forum, and to exchange
information.
Sean James
PCB Designer
Telecast Fiber Systems, Inc.
102 Grove Street
Worcester, MA 01605
(TEL) 508.754.4858 x33
(FAX) 413.541.6170
* * *
hello,
alright, mr. lomax... i seen that comment about making a
brick. hahaha. this board is a wraparound selftest for
an interface device. it plugs in where the device under
test (dut) would and checks copper path. the dut does
indeed have two 63mil boards adhered onto a metal core.
we hav
Have you tried Pads PowerPCB?
John Williams
At 09:03 PM 12/21/01 +1100, you wrote:
>Hello all,
>
>We have been given responsibility for a large suite of technology from a
>defunct US company (once owned by Cadence). The schematics are in OrCad
>capture (DSN) format, but the PCBs are unknow
mr. lomax:
thank you for your comments. if a single board is unobtainable
or way too pricey, i will do like you say and sandwich two 63mil
boards onto a core. i've posted another email on why i'd like
to avoid this.
is the 1-to-3 relationship between via width and via depth the
same for a thr
Michael,
This 'lil project of yours raised an eyebrow over here, so I decided to ask
my favorite prototype house if they could do this... and they said "sure"
So, you might want to give these guys a call.
I've had really good luck with them both on quality and prices, and I don't
usually go aro
Ian,
I did some work for a local company that was a spin-off of Nortel and ran
into the same problem. The schematics were in Cadence but the PCB files were
unknown. I found out later that they were created using a proprietary layout
program of Nortels. It seems that this program is created by Cade
Tango, and Accell used the .pcb file format.
Bill Brooks
PCB Design Engineer , C.I.D.
DATRON WORLD COMMUNICATIONS, INC
3030 Enterprise Court
Vista, CA 92083
Tel: (760)597-1500 Ext 3772 Fax: (760)597-1510
mailto:[EMAIL PROTECTED]
IPC Designers Council, San Diego Chapter
http://www.ipc.org/S
When Protel assigns gerber file name extensions (xx.gxx), what is the
rule for internal layers? I just did a 6 layer board, and the extensions
are. g10, .g1, .g2 & .g5.
When you try to import either a single or batch file, Protel only allows a 3
character extension to be seen, and not a 2 char
At 08:54 AM 12/21/01 -0800, you wrote:
>Tango, and Accell used the .pcb file format.
As do Protel, Zuken Cadstar, and Mentor Expedition (Veribest).
John Williams
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* To post a message: mailto:[EMAIL PROTECTED]
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* To leave this list vis
Why not cut the file in half and post it somewhere for people to view the
binary?
> -Original Message-
> From: Ian Wilson [mailto:[EMAIL PROTECTED]]
> Sent: Friday, December 21, 2001 2:03 AM
> To: [EMAIL PROTECTED]
> Subject: [PEDA] Want to know which program created some .PCB files
>
>
Post the 1st half! :)
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On Mon, 17 Dec 2001, Harry Selfridge wrote:
> After much experimentation, we settled on dual-head Matrox cards. They are
> very stable, and Matrox is constantly improving the firmware and
> drivers. Update downloads are available on the Matrox website at
> reasonably frequent intervals - even
This has been a little screwy for a long time. UNTIL they fix it, you'll
have to rename the 2 digit files such as:
.g1 --> .g01
That allows the gerber read back to get them all.
> -Original Message-
> From: Sean James [mailto:[EMAIL PROTECTED]]
> Sent: Friday, December 21, 2001 10:00 A
Steve,
Your source for danger??? Just a question how it was determined it was
really dual proc
that causes Matrox dual head problems. Its been a while too since I have
used
dual proc and the dual head set up but we never really got ant good info out
of Dell
or Matrox back then.
Robert M. Wolfe, C
Ian,
VeriBest (now Mentor) was one that had a .pcb extension
Robert M. Wolfe, C.I.D.
[EMAIL PROTECTED]
- Original Message -
From: "Ian Wilson" <[EMAIL PROTECTED]>
To: <[EMAIL PROTECTED]>
Sent: Friday, December 21, 2001 5:03 AM
Subject: [PEDA] Want to know which program created some .PCB
What are the first few bytes of the files (10 or so). That shouldn't give
any IP away! There might be a recognisable header...
>>Hello all,
>>
>>We have been given responsibility for a large suite of technology from a
>>defunct US company (once owned by Cadence). The schematics are in OrCad
>>c
Dwight,
I believe it is the first one on the list of footprints it will actually put
on the board.
And the only one it will automatically put on the board.
In my situation I would really like an option to update automatically in one
shot all of the footprints in a board to what is in the library.
I understand that the user group started with local meetings in the San
Jose California area, but there have not been actual meetings for a long
time, except for a few Protel-sponsored meetings at PCB Design Conference
West and East.
Worcester is about an hour away from me and I'd be happy to
I had my Matrox G400DH with my dual PIII 450Mhz Intel based mother board for 1.5
years. The only problem I had was games did not play too smoothly.
If you tell me what your system configuration it, I can solve your Matrox headaches.
Brian Guralnick
- Original Message -
F
At 03:18 PM 12/21/2001 -0500, M. Wahab wrote:
> what is the format of a Protel .PIK file and how would it know
>the units (mils or mm) ?
Assuming Protel 99, the PIK file is controlled by the CAM Manager. A pick
and place generation file is created in the CAM Outputs for [pcbfilename]
folder
At 06:48 PM 12/21/2001 +, Steve Wiseman wrote:
>Danger, Will Robinson! The Matrox drivers, at least unitil very recently
>when I gave up trying, do _not_ work on twin-CPU machines. (I tend to run
>twins, so I can have Specctra battering away in the background, but keep
>on Protelling on the ot
At 02:36 PM 12/21/2001 +1100, Thomas wrote:
>I have a 5 sheet project that I was planning to put on one PCB.
>However It has become clear that there is no way all the parts are going to
>fit in the space available.
>
>To solve this I will have to stack 2 PCBs (there are mounting slots provided
>fo
At 06:26 PM 12/20/2001 -0800, Dennis Saputelli wrote:
>but is it true that to use the synchronizer the schematics have to have
>all the right footprints plugged into the sch symbol?
Someone else answered "Yes." I don't think so. Uncheck "Update Component
Footprints" in the Update PCB dialog.
[E
At 10:34 AM 12/21/2001 -0500, Robison Michael R CNIN wrote:
>is the 1-to-3 relationship between via width and via depth the
>same for a thruhole pad?
From a fabrication point of view, more or less, a via = a thruhole pad.
The plating process is the same.
On the subject of cost, it sounds like
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