I would agree with his statements.. but there is other equally important
considerations.
First thing is use the component centre as the component origin. It will
save you headacks later, Place it on a metric (1mm) grid even if the rest of
the board is placed on an imperial grid. (But move your
I've only got one 300MHz line, and one 200MHz line, the 300MHz is a Thevenin
termination, and the 200MHz is a series termination.
Thanks for the advice.
- Original Message -
From: "Richard Sumner" <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Saturday, September 28
Robison Michael R CNIN wrote:
> Hello,
>
> I've drawn a schematic and now I'm attempting to interactively
> route the traces to match some old artwork, but I've run into
> some guard traces that I haven't got in the schematic. At
> least I think they are guard traces. They have a via to GND
> a
At 09:01 AM 9/27/2002 -0500, Robison Michael R CNIN wrote:
>I've drawn a schematic and now I'm attempting to interactively
>route the traces to match some old artwork, but I've run into
>some guard traces that I haven't got in the schematic. At
>least I think they are guard traces. They have a v
[EMAIL PROTECTED] wrote:
> Run a couple of amps (from a current limited power supply) through the short and
> use a 5 1/2 digit voltmeter on the millivolt range and you can get the short
> circuit location fairly easily.
Yes, that's the procedure. But, with perhaps 500 holes tied to the ground
I recall some option that can be set to "include single-pin nets" -- this
might give you net-names for all those unconnected pins, then the usual
'update primitives from connected copper' (or whatever) would take care of
this. I can't readily test this right now, but maybe it's enough to help...
Juha,
Just looked at your database.
First, your vias are misplaced, and need to be exactly in the center of the
opening between the pads, which appear to be on a 1mm grid, which means that
you vias should be on a .5mm grid. This will keep your vias as far as
possible from the actual BGA pad, and
Juha,
It seems that everyone is missing the primary questions.
What is the speed of the device?
What type of routing are you doing, TTL / CMOS, ECL, LVDS, etc., etc., etc.?
How many of the actual I/O's are you actually using?
Where are all of your I?O's going to or comming from (do most of th
Richard:
Sorry, I guess I didn't read your posting well enough (once is not always
enough!).
We didn't need to worry about this stuff back in the days of TTL and
metal-gate CMOS. I used to see big, long backplanes with big, bold tracks
on 2-sided PCBs, and big, long stubs (plug-in cards), and i
Ivan,
I agree completely. However I did note that clocks and strobes should be
clean, perhaps not emphatically enough though!
One way to reduce the overshoot on an unterminated trace is to really load
the drivers. For example, by making the trace Z as low as you can (a wide
trace and a small
Miker,
I belive if you were to _first_ place your via such that it only cuts
through the ground plane and not any other copper, then the via will
automatically picks up GND as its net assignment. Now, if you start
placing your guard traces _starting from the via_ then those too would
automati
We need to come up with some kind of online blacklist (or whitelist) of PCB
fabs. I certainly would not want to be a victim of inadequate (or
fraudulent) board testing. How could we do this? Some sort of blog with
anecdotal entries?
Best regards,
Ivan Baggett
Bagotronix Inc.
website: www.bago
> The rise time is not as important as you might think. You said 30 MHz is
I disagree. The problem is when you have devices that are clocked by
strobes. Enough ringing on that strobe can cause metastability and/or
multiple clocking. If the ringing is bad enough to cause a non-monotonic
transit
Hello,
I just created a one pin schematic part. Called a guard and connected the
pin to ground in the schematic. The footprint for this part is just a
through hole pad. I hope the this helps.
-Original Message-
From: Robison Michael R CNIN [mailto:[EMAIL PROTECTED]]
Sent: F
Hello,
I've drawn a schematic and now I'm attempting to interactively
route the traces to match some old artwork, but I've run into
some guard traces that I haven't got in the schematic. At
least I think they are guard traces. They have a via to GND
at one end and follow beside another trace fo
Brian,
The rise time is not as important as you might think. You said 30 MHz is
the frequency. If that means that there is 30 nanoseconds between edges,
you can probably ignore terminations on the data lines. There will be some
ringing for a few reflection times (perhaps 5-10 ns) but then the
Try doing a model in Protel using the signal integrity function.
Don't try the whole bus, just one circuit, get the IO technology, lengths,
widths, shape and board
layup and material correct and you'll get a reasonably close simulation - or
at least I did.
Assuming you're not going to let more t
Unfortuneately not. I've got the trial version of HyperLynx here, but it
doesn't allow the simulation of custom made setups. I've had a couple of
setups simulated by a contact in the industry that has access to the full
version, this is what put me onto needing the termination. However, it
isn'
How would you even solder a 1020pin BGA (I assume that's 32x32 with the four
central balls missing?)
I say that you'd need to use blind vias, with a lot of layers (I've never
worked on BGA's but would imagine that you might get 4rows/columns per
layer). My estimate would require around 8layers.
Hei Juha,
I currently don't have the time to work out a detailed routing strategy, but if
I hear of such a biest I would consider blind/buried vias. If you choose to go
to microvias you even can place them within the BGA pads! Depending the overall
complexity I would recommend a 2+N+2 stack in
Thomas,
but what kind of signal do you want to model with the 'PWLR' ? Is it a
voltage like with VPWL or a current as with IPWL (with time/value pairs as
parameters) ? Where can i find this part 'PWLR', where can i find the
library you got it from (what .ddb is it in) ? Maybe the 'PWLR' does take
Hi again,
<> What is the best PCB layer stack for
this type of BGA? <>
http://groups.yahoo.com/group/protel-users/files/junk/
There is 1020-pin 1mm pitch BGA. It would be very
pleasing to have some information and help how to
route that huge BGA. What are trace width and cap
between different t
Hi,
I just uploaded 1020-BGA_ROUTING_TEST.ddb here
http://groups.yahoo.com/group/protel-users/files/junk/
There is 1020-pin 1mm pitch BGA. It would be very
pleasing to have some information and help how to
route that huge BGA. What are trace width and cap
between different tracks and so...
It w
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