Re: [PEDA] Video Board Recommendations ?

I'm using an nVidia Quadro FX 500. No problems so far. Dave -Original Message- From: Joe Sapienza [mailto:[EMAIL PROTECTED] Sent: 26 August 2004 03:53 To: Protel EDA Forum Subject: Re: [PEDA] Video Board Recommendations ? any feedback on the Nvidia FX 700, been thinking about it and

Re: [PEDA] Board fabricator in UK/EU

Steve, Have you tried any of the PCB manufacturers on Premiers (Protel UK distributor)web site? http://www.eda.co.uk/servProv.html#PCBManufacturing Regards, Dave -Original Message- From: Stephen Casey [mailto:[EMAIL PROTECTED] Sent: 11 September 2003 12:50 To: Protel forum Subject:

Re: [PEDA] File name way too long on schematic

Charlie, Look under PLACE-ANNOTATION Hit tab and select .DOC_FILE_NAME_NO_PATH in the text box. Hope this helps. Dave Buckley -Original Message- From: Jenkins, Charlie [mailto:[EMAIL PROTECTED]] Sent: 16 August 2002 13:13 To: 'PEDA' Subject: [PEDA] File name way too long on

Re: [PEDA] DXP NOT MADE FOR WINDOWS NT

Thats interesting I tried it on NT and it just bombed complaining about a missing .dll Dave -Original Message- From: Rene Tschaggelar [mailto:[EMAIL PROTECTED]] Sent: 31 July 2002 09:02 To: Protel EDA Forum Subject: Re: [PEDA] DXP NOT MADE FOR WINDOWS NT I got a quote

Re: [PEDA] Speaking of Protel Bugs.

I guess this means we should write the time as minutes/seconds/hours then ;-) Dave Buckley -Original Message- From: Bagotronix Tech Support [mailto:[EMAIL PROTECTED]] Sent: 23 July 2002 15:24 To: Protel EDA Forum Subject: Re: [PEDA] Speaking of Protel Bugs. rant on I also don't

Re: [PEDA] FW: Access violation -- Is it a Protel bug?

I have tried to reproduce this behaviour by creating a schematic symbol which is associated with footprint BLANK. No ERC errors in the schematic. Generating a PCB using PCB WIZARD and using UPDATE PCB does not cause a problem. The updated PCB displays two of 6 components (not including the BLANK)

Re: [PEDA] FW: Access violation -- Is it a Protel bug?

that are blank (that is have no entities). Ian Wilson On 03:33 AM 18/04/2002 -0700, Buckley.Dave said: I have tried to reproduce this behaviour by creating a schematic symbol which is associated with footprint BLANK. No ERC errors in the schematic. Generating a PCB using PCB WIZARD and using UPDATE PCB

Re: [PEDA] net connections for a fill ?

miker, I think you might want to try placing a polygon plane instead of a fill. Polygon planes provide thermal relief and don't connect to other nets. Cheers, Dave Buckley -Original Message- From: Robison Michael R CNIN [mailto:[EMAIL PROTECTED]] Sent: 18 April 2002 14:40 To: 'Protel

Re: [PEDA] net connections for a fill ?

-Original Message- From: Robison Michael R CNIN [mailto:[EMAIL PROTECTED]] Sent: 18 April 2002 15:41 To: 'Protel EDA Forum' Subject: Re: [PEDA] net connections for a fill ? miker, I think you might want to try placing a polygon plane instead of a fill. Polygon planes provide thermal

Re: [PEDA] License number not accepted

I don't know if it's a UK license problem but I tried registering last week and failed. Tried again today and no problem. Dave -Original Message- From: Andrew Ircha [mailto:[EMAIL PROTECTED]] Sent: 17 December 2001 10:18 To: Protel EDA Forum Subject: [PEDA] License number not accepted

Re: [PEDA] Removal From List

Jim, I had one today. Our IT dept say it's not them. Dave Buckley -Original Message- From: Jim McGrath [mailto:[EMAIL PROTECTED]] Sent: 06 September 2001 18:45 To: Protel EDA Forum Subject: [PEDA] Removal From List Hi All, Has Anyone else received this messege? Last time I got this

Re: [PEDA] auto-routing layers

Try Design-Rules-Routing-Routing layers. Dave -Original Message- From: Michael Reynolds [mailto:[EMAIL PROTECTED]] Sent: 13 March 2001 16:04 To: 'Protel EDA Forum' Subject: Re: [PEDA] auto-routing layers Where is the layer setup in the DRC? The only thing that I can think of is that