t: Re: [PEDA] Specctra 10.2 Interfaces with 99SE
13/06/2003 22:51:09, Shuping Lew <[EMAIL PROTECTED]> wrote:
>Have anybody use Protel99SE interfaces with Specctra 10.2?
Yes - works fine. (Still the same old via hole size issues). I was forced to
give Cadence a pile of money, si
interfaces with Specctra 10.2?
Thank you very much...
Shuping Lew
Quintron Systems, Inc.
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y has experienced that problem, and any work around for that
problem. Thank you for any reply in advance...
Shuping Lew
Quintron Systems, Inc
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: Protel EDA Forum
Subject: Re: [PEDA] Fan out Via clearance
Shuping Lew wrote:
> Jon, Thank you very much for your replied.
>
> Could you describe some more details? ---How to set up different grids
> for Vias and traces? Grid setting for traces should be much smaller
than
> Via&#
g
good
(and maybe adjust manually, too!), make a backup copy of your PCB, then
change your grid/rules for track spacing, and run the autorouter will
all
the other passes checked, making sure you have "Lock all preroutes"
checked.
-Original Message-
From: Shuping Lew [mailto:[EMAIL
--Original Message-
From: Jon Elson [mailto:[EMAIL PROTECTED]]
Sent: Tuesday, October 15, 2002 12:38 PM
To: Protel EDA Forum
Subject: Re: [PEDA] Fan out Via clearance
Shuping Lew wrote:
> Hello, all,
>
> I am using Protel 99Se Auto router for fan out Vias. I'd like to have
>
Hello, all,
I am using Protel 99Se Auto router for fan out Vias. I'd like to have
one trace go in between fan out vias. Is there a rule to set it up?
Thank you very much!
Shuping Lew
Quintron Systems, Inc.
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* To post a me
Never mind. I found the problem. Thank you.
> -Original Message-
> From: Shuping Lew
> Sent: Wednesday, October 09, 2002 2:44 PM
> To: '[EMAIL PROTECTED]'
> Subject: Fan out vias from surface mount component pads
>
> Hi, all,
>
>
happen. Design rules were
set for 13/30 for via, 7mil trace w/ 6 mil clearance, and top and bottom
layers only. Why doesn't it work? Am I missing something?
I am using Protel 99SE.
Thank you for any reply...
Shuping Lew
Quintron Systems
Dear Waldemar,
Thank you for your replied.
I tried the first comment, it works. Thank you.
I still have problem setting up SMD pads to polygon connection. Here is
what I did:
Design rule/manufacturing/polygon connect style, I tried to use Pad
Specification as filter. There is no Object Type
Hello, All,
I need to put a polygon plane on the bottom layer.
1. I'd like to set up the clearance of the plane different from the
regular trace of the board, which is 12mil instead of 7 mil for regular
trace connection.
2. I also like to set up the polygon connects to fan out via instead of
di
Hello, All,
I need to put a polygon plane on the bottom layer.
1. I'd like to set up the clearance of the plane different from the
regular trace of the board, which is 12mil instead of 7 mil for regular
trace connection.
2. I also like to set up the polygon connects to fan out via instead of
di
For rectangular shape, just simply use PLACE/FILL to place a filling to
negative layer. To place other shapes, use PLACE/POLYGON, set up grid
size equal or smaller than track width to get a solid plane. Hope this
will help.
Shuping
-Original Message-
From: Watnoski, Michael [mailto:[EMAI
w how to start.
Can you give me some basic steps or guidelines for this topic?
P.S. It is 6 layers board(4 signal and 2 planes). Impedance is 100 ohms.
Thank you very much!
Shuping Lew
Quintron Systems, Inc
* Tra
Thank you. ABD. I like the idea.
Shuping
-Original Message-
From: Abd ulRahman Lomax [mailto:[EMAIL PROTECTED]]
Sent: Wednesday, April 17, 2002 3:21 PM
To: Protel EDA Forum
Subject: Re: [PEDA] FW: Access violation -- Is it a Protel bug?
At 02:40 PM 4/17/2002 -0700, Shuping Lew wrote
I use some notes on every schematic project. So I created a schematic symbol
named "note" for it. To avoid the warning of missing footprint, I also
created a footprint named "blank" to associate with that symbol. For some
reason, Protel does not like the footprint "Blank"(there is not primitive on
Forum
Subject: Re: [PEDA] FW: Access violation -- Is it a Protel bug?
At 10:13 AM 4/17/2002 -0700, Shuping Lew wrote:
>---I created netlist for each sheets. There are total 25 sheets. I then
>loaded them individaully. There were no problem.
If the problem was, for example, that you had an inc
Dear ABD,
First of all, yes, I would strongly suspect a bug, though a damaged
executable is a possible but unlikely culprit. Mr. Wilson is correct, it
should not be possible to cause an access violation with bad (or good)
netlist data.
One factor not stated so far: did the Schematic pass a ful
ccess violation -- Is it a Protel bug?
On 03:23 PM 16/04/2002 -0700, Shuping Lew said:
>I tried to load a netlist file to PCB. It has over 1,100 components. I
>receiced a warning of access violation. It says: Access Violation at
address
>OF086CC6 module Exception Occurred in PCB: N
t itself having duplicate
Identifiers first. It only takes one.
Brian
At 03:23 PM 4/16/02 -0700, you wrote:
>
>
> -Original Message-
>From: Shuping Lew [mailto:[EMAIL PROTECTED]]
>Sent: Tuesday, April 16, 2002 2:51 PM
>To:'[EMAIL PROTECTED]'
>Subject:
Warning
Unable to process data:
multipart/mixed;boundary="=_NextPart_000_0005_01C1E55A.A530A310"
Thank to everybody. I tried it out. It works! Save me some time.
Shuping
-Original Message-
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]]
Sent: Monday, April 08, 2002 5:46 PM
To: Protel EDA Forum
Subject: Re: [PEDA] Excel to Protel Schematic
You could use a screen capture and just
, Shuping Lew said:
>Does anybody know how to import a Microsoft Excel 2000 format file into
>Protel Schematic?
Shuping,
Can you explain what you mean by "import and Excel file into Sch"? Do you
mean just import component attributes (part type, footprint etc) or do you
mean
Hello, there.
Does anybody know how to import a Microsoft Excel 2000 format file into
Protel Schematic?
Thank you.
Shuping
Quintron Systems, Inc
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Thanks. Ian.
-Original Message-
From: Ian Wilson [mailto:[EMAIL PROTECTED]]
Sent: Monday, December 17, 2001 4:50 PM
To: Protel EDA Forum
Subject: Re: [PEDA] Bring out un-connected pins
At 03:55 PM 17/12/01 -0800, you wrote:
>Hello, all.
>I recalled the same question was discussed coup
Hello, all.
I recalled the same question was discussed couple weeks ago but I couldn't
find those e-mail anymore.
How should I set up the design rule so I can get rid of all the violations
for bring out any unconnected pins to vias?
Thank you very much.
Susan Lew
Quintron Systems, Inc.
*
lid there.
You could try Protel support, too; or reinstall.
Dwight.
-Original Message-
From: Shuping Lew [mailto:[EMAIL PROTECTED]]
Sent: Thursday, December 13, 2001 1:04 PM
No, The board is placed but not rounted yet. But I did load the netlist into
the PCB few times. At first the net
nets which causes the
ratsnest line to turn into a dashed line.
Regards,
Casey Vanderweide.
- Original Message -
From: "Shuping Lew" <[EMAIL PROTECTED]>
To: "'Protel EDA Forum'" <[EMAIL PROTECTED]>
Sent: Thursday, December 13, 2001 9:15 AM
Subject:
Email:[EMAIL PROTECTED]
Australia
___
"Shuping Lew" <[EMAIL PROTECTED]> on 12/13/2001 04:06:41 AM
Please respond to "Protel EDA Forum" <[EMAIL PROTECTED]>
To: "Protel EDA Forum" &
Warning
Unable to process data:
multipart/mixed;boundary="=_NextPart_000_0004_01C182F4.B2BF7F10"
The problem I ran into is designator annotation when different kind of
graphic multi-part component is made. Protel can not identify which parts
are belong to the same component. It will go U1A, U1B...then U2A,
U2B...Sometime it brings in the wrong part.
Any work around? Thanks.
Susan
Quintron
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