Hi! We're using a 44 pin Xilinx CPLD to interface a MAX2769 GPS receiver to an STM32F407 microcontroller. Specifically, it takes:
- 4 parallel bits from the GPS which change at 4.096 MHz - A 16.384 MHz clock from the GPS - A 25 MHz clock from the STM32 ... and then outputs the 4 bits as a 8 bit 25 Mbps SPI to the STM32. K is working on the Verilog, and it's probably going to work out just great. The funny part is that Jamey and I thought about it a bit, and realized you could do it in 5x 16 pin discreet logic chips. You, or your discreet logic obsessed friends, are welcome to give this a try! I'll even buy the chips for you. Terrible picture attached. Anyone want to try? Let me know! Andrew -- ------------------------------------------------------- Andrew Greenberg Electrical and Computer Engineering Portland State University http://www.ece.pdx.edu/ a...@ece.pdx.edu C: 503.708.7711 -------------------------------------------------------
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