Author: David Schneider <david.schnei...@picle.org> Branch: fast-slowpath Changeset: r65612:e79bad52356d Date: 2013-07-24 10:22 -0500 http://bitbucket.org/pypy/pypy/changeset/e79bad52356d/
Log: add ARM support for cond_call diff --git a/rpython/jit/backend/arm/assembler.py b/rpython/jit/backend/arm/assembler.py --- a/rpython/jit/backend/arm/assembler.py +++ b/rpython/jit/backend/arm/assembler.py @@ -259,6 +259,23 @@ else: self.wb_slowpath[withcards + 2 * withfloats] = rawstart + def _build_cond_call_slowpath(self, supports_floats, callee_only): + """ This builds a general call slowpath, for whatever call happens to + come. + """ + mc = InstrBuilder(self.cpu.cpuinfo.arch_version) + # + self._push_all_regs_to_jitframe(mc, [], self.cpu.supports_floats, callee_only) + ## args are in their respective positions + mc.PUSH([r.ip.value, r.lr.value]) + mc.BLX(r.r4.value) + self._reload_frame_if_necessary(mc) + self._pop_all_regs_from_jitframe(mc, [], supports_floats, + callee_only) + # return + mc.POP([r.ip.value, r.pc.value]) + return mc.materialize(self.cpu.asmmemmgr, []) + def _build_malloc_slowpath(self, kind): """ While arriving on slowpath, we have a gcpattern on stack 0. The arguments are passed in r0 and r10, as follows: diff --git a/rpython/jit/backend/arm/opassembler.py b/rpython/jit/backend/arm/opassembler.py --- a/rpython/jit/backend/arm/opassembler.py +++ b/rpython/jit/backend/arm/opassembler.py @@ -301,6 +301,32 @@ self._check_frame_depth_debug(self.mc) return fcond + def cond_call(self, op, gcmap, cond_loc, call_loc, fcond): + assert call_loc is r.r4 + self.mc.TST_rr(cond_loc.value, cond_loc.value) + jmp_adr = self.mc.currpos() + self.mc.BKPT() # patched later + # + self.push_gcmap(self.mc, gcmap, store=True) + # + callee_only = False + floats = False + if self._regalloc is not None: + for reg in self._regalloc.rm.reg_bindings.values(): + if reg not in self._regalloc.rm.save_around_call_regs: + break + else: + callee_only = True + if self._regalloc.vfprm.reg_bindings: + floats = True + cond_call_adr = self.cond_call_slowpath[floats * 2 + callee_only] + self.mc.BL(cond_call_adr) + self.pop_gcmap(self.mc) + # never any result value + pmc = OverwritingBuilder(self.mc, jmp_adr, WORD) + pmc.B_offs(self.mc.currpos(), c.EQ) # equivalent to 0 as result of TST above + return fcond + def emit_op_jump(self, op, arglocs, regalloc, fcond): target_token = op.getdescr() assert isinstance(target_token, TargetToken) diff --git a/rpython/jit/backend/arm/regalloc.py b/rpython/jit/backend/arm/regalloc.py --- a/rpython/jit/backend/arm/regalloc.py +++ b/rpython/jit/backend/arm/regalloc.py @@ -164,7 +164,11 @@ def get_scratch_reg(self, type=INT, forbidden_vars=[], selected_reg=None): assert type == INT or type == REF - box = TempBox() + box = None + if type == INT: + box = TempInt() + else: + box = TempPtr() self.temp_boxes.append(box) reg = self.force_allocate_reg(box, forbidden_vars=forbidden_vars, selected_reg=selected_reg) @@ -1126,6 +1130,24 @@ prepare_op_cond_call_gc_wb_array = prepare_op_cond_call_gc_wb + def prepare_op_cond_call(self, op, fcond): + assert op.result is None + assert 2 <= op.numargs() <= 4 + 2 + tmpreg = self.get_scratch_reg(INT, selected_reg=r.r4) + v = op.getarg(1) + assert isinstance(v, Const) + imm = self.rm.convert_to_imm(v) + self.assembler.regalloc_mov(imm, tmpreg) + args_so_far = [] + for i in range(2, op.numargs()): + reg = r.argument_regs[i - 2] + arg = op.getarg(i) + self.make_sure_var_in_reg(arg, args_so_far, selected_reg=reg) + args_so_far.append(arg) + loc_cond = self.make_sure_var_in_reg(op.getarg(0), args_so_far) + gcmap = self.get_gcmap([tmpreg]) + self.assembler.cond_call(op, gcmap, loc_cond, tmpreg, fcond) + def prepare_op_force_token(self, op, fcond): # XXX for now we return a regular reg res_loc = self.force_allocate_reg(op.result) _______________________________________________ pypy-commit mailing list pypy-commit@python.org http://mail.python.org/mailman/listinfo/pypy-commit