Author: Richard Plangger <planri...@gmail.com> Branch: s390x-backend Changeset: r82069:f5ccdddddea0 Date: 2016-02-04 10:04 +0100 http://bitbucket.org/pypy/pypy/changeset/f5ccdddddea0/
Log: an edge case in call release gil that could overwrite values for registers r8-r13, because the stack is not decremented accordingly diff --git a/rpython/jit/backend/zarch/callbuilder.py b/rpython/jit/backend/zarch/callbuilder.py --- a/rpython/jit/backend/zarch/callbuilder.py +++ b/rpython/jit/backend/zarch/callbuilder.py @@ -263,8 +263,13 @@ self.mc.LGR(RSAVEDRES, reg) elif reg.is_fp_reg(): self.mc.STD(reg, l.addr(16*WORD, r.SP)) + # r8-r13 live on the stack and must NOT be overwritten, + # restore_stack_pointer already moved SP + subtracted_to_sp, + self.mc.LAY(r.SP, l.addr(-self.subtracted_to_sp, r.SP)) self.mc.load_imm(self.mc.RAW_CALL_REG, self.asm.reacqgil_addr) self.mc.raw_call() + self.mc.LAY(r.SP, l.addr(self.subtracted_to_sp, r.SP)) + if reg is not None: if reg.is_core_reg(): self.mc.LGR(reg, RSAVEDRES) _______________________________________________ pypy-commit mailing list pypy-commit@python.org https://mail.python.org/mailman/listinfo/pypy-commit