Author: Richard Plangger <planri...@gmail.com>
Branch: s390x-backend
Changeset: r80335:2b4c4bd98951
Date: 2015-10-19 15:29 +0200
http://bitbucket.org/pypy/pypy/changeset/2b4c4bd98951/

Log:    called first subroutine in assembler

diff --git a/rpython/jit/backend/zarch/assembler.py 
b/rpython/jit/backend/zarch/assembler.py
--- a/rpython/jit/backend/zarch/assembler.py
+++ b/rpython/jit/backend/zarch/assembler.py
@@ -50,11 +50,12 @@
         return clt.asmmemmgr_blocks
 
     def gen_func_prolog(self):
-        self.mc.STMG(reg.r0, reg.r15, loc.addr(reg.sp, -160))
-        #self.mc.LAY(reg.r15, loc.addr(reg.sp, -160))
+        self.mc.STMG(reg.r11, reg.r15, loc.addr(reg.sp, -96))
+        self.mc.AHI(reg.sp, loc.imm(-96))
+        #self.mc.LAY(reg.r15, loc.addr(reg.sp, -))
 
     def gen_func_epilog(self):
-        self.mc.LMG(reg.r0, reg.r15, loc.addr(reg.sp, -160))
+        self.mc.LMG(reg.r11, reg.r15, loc.addr(reg.sp, 0))
         self.jmpto(reg.r14)
 
     def jmpto(self, register):
diff --git a/rpython/jit/backend/zarch/locations.py 
b/rpython/jit/backend/zarch/locations.py
--- a/rpython/jit/backend/zarch/locations.py
+++ b/rpython/jit/backend/zarch/locations.py
@@ -173,7 +173,7 @@
     def __init__(self, basereg, indexreg, displace):
         self.base = basereg.value
         self.displace = displace
-        self.index = -1
+        self.index = 0 # designates the absense of an index register!
         if indexreg:
             self.index = indexreg.value
 
diff --git a/rpython/jit/backend/zarch/test/test_assembler.py 
b/rpython/jit/backend/zarch/test/test_assembler.py
--- a/rpython/jit/backend/zarch/test/test_assembler.py
+++ b/rpython/jit/backend/zarch/test/test_assembler.py
@@ -1,7 +1,7 @@
 from rpython.jit.backend.zarch import conditions as con
 from rpython.jit.backend.zarch import registers as reg
 from rpython.jit.backend.zarch.assembler import AssemblerZARCH
-from rpython.jit.backend.zarch.locations import imm
+from rpython.jit.backend.zarch import locations as loc
 from rpython.jit.backend.zarch.test.support import run_asm
 from rpython.jit.backend.detect_cpu import getcpuclass
 from rpython.jit.metainterp.resoperation import rop
@@ -36,13 +36,28 @@
             is AssemblerZARCH.emit_op_int_add.im_func
 
     def test_load_small_int_to_reg(self):
-        self.a.mc.LGHI(reg.r2, imm(123))
+        self.a.mc.LGHI(reg.r2, loc.imm(123))
         self.a.jmpto(reg.r14)
         assert run_asm(self.a) == 123
 
-    #def test_load_small_int_to_reg_func(self):
-    #    self.a.gen_func_prolog()
-    #    self.a.mc.LGHI(r.r2, imm(123))
-    #    self.a.gen_func_epilog()
-    #    assert run_asm(self.a) == 123
+    def test_prolog_epilog(self):
+        self.a.gen_func_prolog()
+        self.a.mc.LGHI(reg.r2, loc.imm(123))
+        self.a.gen_func_epilog()
+        assert run_asm(self.a) == 123
 
+    def test_simple_func(self):
+        # enter
+        self.a.mc.STMG(reg.r11, reg.r15, loc.addr(reg.sp, -96))
+        self.a.mc.AHI(reg.sp, loc.imm(-96))
+        self.a.mc.BRASL(reg.r14, loc.imm(8+6))
+        self.a.mc.LMG(reg.r11, reg.r15, loc.addr(reg.sp, 0))
+        self.a.jmpto(reg.r14)
+
+        addr = self.a.mc.get_relative_pos()
+        assert addr & 0x1 == 0
+        self.a.gen_func_prolog()
+        self.a.mc.LGHI(reg.r2, loc.imm(321))
+        self.a.gen_func_epilog()
+        assert run_asm(self.a) == 321
+
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