[pypy-commit] pypy vecopt: finished impl of float_ne with guards

Author: Richard Plangger r...@pasra.at Branch: vecopt Changeset: r78706:924ff20716c0 Date: 2015-07-29 13:00 +0200 http://bitbucket.org/pypy/pypy/changeset/924ff20716c0/ Log:finished impl of float_ne with guards diff --git a/rpython/jit/backend/x86/vector_ext.py

[pypy-commit] pypy vecopt: bool(0.1) return True, in the jit bool(0.1) transforms to cast_float_to_int which is wrong,

Author: Richard Plangger r...@pasra.at Branch: vecopt Changeset: r78703:4fead7c7623f Date: 2015-07-29 11:46 +0200 http://bitbucket.org/pypy/pypy/changeset/4fead7c7623f/ Log:bool(0.1) return True, in the jit bool(0.1) transforms to cast_float_to_int which is wrong, updated the

[pypy-commit] pypy default: added test to check if cast single float to bool is working properly aswell

Author: Richard Plangger r...@pasra.at Branch: Changeset: r78705:d221a50d7898 Date: 2015-07-29 12:15 +0200 http://bitbucket.org/pypy/pypy/changeset/d221a50d7898/ Log:added test to check if cast single float to bool is working properly aswell diff --git

[pypy-commit] pypy vecopt: all but 2 vectoriztion tests passing again. the scheduling that prefers pure operations messes up these test cases

Author: Richard Plangger r...@pasra.at Branch: vecopt Changeset: r78696:08d59f3ff88c Date: 2015-07-28 18:45 +0200 http://bitbucket.org/pypy/pypy/changeset/08d59f3ff88c/ Log:all but 2 vectoriztion tests passing again. the scheduling that prefers pure operations messes up these test

[pypy-commit] pypy vecopt: restricted the test environment, loop versioning only works resumedescr (not basicfaildescr)

Author: Richard Plangger r...@pasra.at Branch: vecopt Changeset: r78695:fce17b8ec26a Date: 2015-07-28 17:02 +0200 http://bitbucket.org/pypy/pypy/changeset/fce17b8ec26a/ Log:restricted the test environment, loop versioning only works resumedescr (not basicfaildescr) rawstart is now

[pypy-commit] pypy vecopt: stripping sse4 of the model returned from host platform in the test to pass it (c compiler will never append sse4)

Author: Richard Plangger r...@pasra.at Branch: vecopt Changeset: r78698:152353977ab7 Date: 2015-07-28 20:29 +0200 http://bitbucket.org/pypy/pypy/changeset/152353977ab7/ Log:stripping sse4 of the model returned from host platform in the test to pass it (c compiler will never append

[pypy-commit] pypy vecopt: could end in a finish operation, crashed the optimizer

Author: Richard Plangger r...@pasra.at Branch: vecopt Changeset: r78751:c83f61da5f2d Date: 2015-08-03 08:22 +0200 http://bitbucket.org/pypy/pypy/changeset/c83f61da5f2d/ Log:could end in a finish operation, crashed the optimizer diff --git a/rpython/jit/metainterp/history.py

[pypy-commit] pypy vecopt-merge: merged default into vecopt (vecopt-merge)

Author: Richard Plangger r...@pasra.at Branch: vecopt-merge Changeset: r78880:e7b774925efd Date: 2015-08-10 17:20 +0200 http://bitbucket.org/pypy/pypy/changeset/e7b774925efd/ Log:merged default into vecopt (vecopt-merge) diff too long, truncating to 2000 out of 30123 lines diff --git

[pypy-commit] pypy vecopt-merge: added missing vectorize=True for the jit drivers in loop.py

Author: Richard Plangger r...@pasra.at Branch: vecopt-merge Changeset: r78881:4dcddb2caee3 Date: 2015-08-11 11:59 +0200 http://bitbucket.org/pypy/pypy/changeset/4dcddb2caee3/ Log:added missing vectorize=True for the jit drivers in loop.py diff --git a/pypy/module/micronumpy/compile.py

[pypy-commit] pypy vecopt-merge: meeeh, syntax error did not pay attentation to the indentation in this file

Author: Richard Plangger r...@pasra.at Branch: vecopt-merge Changeset: r78886:69fe04c7e304 Date: 2015-08-11 12:42 +0200 http://bitbucket.org/pypy/pypy/changeset/69fe04c7e304/ Log:meeeh, syntax error did not pay attentation to the indentation in this file diff --git

[pypy-commit] pypy vecopt-merge: Backed out changeset 9299faf9cad1

Author: Richard Plangger r...@pasra.at Branch: vecopt-merge Changeset: r78884:18e7a066f96f Date: 2015-08-11 12:24 +0200 http://bitbucket.org/pypy/pypy/changeset/18e7a066f96f/ Log:Backed out changeset 9299faf9cad1 diff --git a/pypy/objspace/std/boolobject.py b/pypy/objspace/std/boolobject.py

[pypy-commit] pypy vecopt-merge: added out_dim to the list of attributes

Author: Richard Plangger r...@pasra.at Branch: vecopt-merge Changeset: r78889:9b128f66714b Date: 2015-08-11 14:38 +0200 http://bitbucket.org/pypy/pypy/changeset/9b128f66714b/ Log:added out_dim to the list of attributes diff --git a/pypy/module/micronumpy/strides.py

[pypy-commit] pypy vecopt-merge: added branch description for vecopt and vecopt-merge

Author: Richard Plangger r...@pasra.at Branch: vecopt-merge Changeset: r78899:98e339e44deb Date: 2015-08-11 16:39 +0200 http://bitbucket.org/pypy/pypy/changeset/98e339e44deb/ Log:added branch description for vecopt and vecopt-merge diff --git a/pypy/doc/whatsnew-head.rst

[pypy-commit] pypy vecopt-merge: passing None to space.call_method is a bad idea

Author: Richard Plangger r...@pasra.at Branch: vecopt-merge Changeset: r78922:5ba373083b5c Date: 2015-08-11 18:20 +0200 http://bitbucket.org/pypy/pypy/changeset/5ba373083b5c/ Log:passing None to space.call_method is a bad idea diff --git a/pypy/module/micronumpy/ufuncs.py

[pypy-commit] pypy vecopt-merge: started to refactor scheduling to remove the unnecessary list allocation each iteration

Author: Richard Plangger r...@pasra.at Branch: vecopt-merge Changeset: r78928:8bbff2ecdaa3 Date: 2015-08-11 19:18 +0200 http://bitbucket.org/pypy/pypy/changeset/8bbff2ecdaa3/ Log:started to refactor scheduling to remove the unnecessary list allocation each iteration diff --git

[pypy-commit] pypy vecopt: missing update pack of nodes scheduled some nodes as a non packed operation (wrong obviously)

Author: Richard Plangger r...@pasra.at Branch: vecopt Changeset: r78843:e8a74e18fc6e Date: 2015-08-07 10:50 +0200 http://bitbucket.org/pypy/pypy/changeset/e8a74e18fc6e/ Log:missing update pack of nodes scheduled some nodes as a non packed operation (wrong obviously) diff --git

[pypy-commit] pypy vecopt-merge-iterator-sharing: started to transform call2 to share iterators in the loop, works but needs check if the jit codes improve as well

Author: Richard Plangger r...@pasra.at Branch: vecopt-merge-iterator-sharing Changeset: r78985:3cc178b04857 Date: 2015-08-14 13:24 +0200 http://bitbucket.org/pypy/pypy/changeset/3cc178b04857/ Log:started to transform call2 to share iterators in the loop, works but needs check if the

[pypy-commit] pypy vecopt-merge-opt: new branch to enhance some places of the optimization

Author: Richard Plangger r...@pasra.at Branch: vecopt-merge-opt Changeset: r78984:a82264bddcac Date: 2015-08-12 12:00 +0200 http://bitbucket.org/pypy/pypy/changeset/a82264bddcac/ Log:new branch to enhance some places of the optimization diff --git

[pypy-commit] pypy vecopt-merge-iterator-sharing: (plan_rich, ronan) first working version that generates all five possible call2 combinations that shares the iterators

Author: Richard Plangger r...@pasra.at Branch: vecopt-merge-iterator-sharing Changeset: r78988:690ba1eaa6a8 Date: 2015-08-14 18:50 +0200 http://bitbucket.org/pypy/pypy/changeset/690ba1eaa6a8/ Log:(plan_rich, ronan) first working version that generates all five possible call2

[pypy-commit] pypy vecopt: ironed out problems indicated by buildbot (small batch)

Author: Richard Plangger r...@pasra.at Branch: vecopt Changeset: r78680:2a58825eefba Date: 2015-07-27 12:09 +0200 http://bitbucket.org/pypy/pypy/changeset/2a58825eefba/ Log:ironed out problems indicated by buildbot (small batch) llgraph now checks for box is equal to zero (otherwise

[pypy-commit] pypy vecopt: using pygame viewer for the dependencies instead of writing it manually to the tmp folder (thx fijal for hint)

Author: Richard Plangger r...@pasra.at Branch: vecopt Changeset: r78682:d3b2ba395def Date: 2015-07-27 12:48 +0200 http://bitbucket.org/pypy/pypy/changeset/d3b2ba395def/ Log:using pygame viewer for the dependencies instead of writing it manually to the tmp folder (thx fijal for hint)

[pypy-commit] pypy vecopt: picked lltype.cast changes for cast to bool, implemented int_is_true as a vector operation

Author: Richard Plangger r...@pasra.at Branch: vecopt Changeset: r78679:658ac4e3b571 Date: 2015-07-27 11:48 +0200 http://bitbucket.org/pypy/pypy/changeset/658ac4e3b571/ Log:picked lltype.cast changes for cast to bool, implemented int_is_true as a vector operation diff --git

[pypy-commit] pypy vecopt: added clone to a descriptor. I used invent_fail_descr before that, which did the same thing, but in a huge switch statement

Author: Richard Plangger r...@pasra.at Branch: vecopt Changeset: r78578:a05aff84b29f Date: 2015-07-17 15:28 +0200 http://bitbucket.org/pypy/pypy/changeset/a05aff84b29f/ Log:added clone to a descriptor. I used invent_fail_descr before that, which did the same thing, but in a huge

[pypy-commit] pypy vecopt: minor simplifications, fixed some tests cases (more to go), the additional abc opt removes some opts, the tests should not check for equivalence of all instructions, but che

Author: Richard Plangger r...@pasra.at Branch: vecopt Changeset: r78579:aa9a9d9cc94b Date: 2015-07-17 16:37 +0200 http://bitbucket.org/pypy/pypy/changeset/aa9a9d9cc94b/ Log:minor simplifications, fixed some tests cases (more to go), the additional abc opt removes some opts, the tests

[pypy-commit] pypy vecopt: trace versioning now compiles each version just once, and attaches patches all further guards to the bridge

Author: Richard Plangger r...@pasra.at Branch: vecopt Changeset: r78584:0d1dc4ba30d3 Date: 2015-07-17 17:19 +0200 http://bitbucket.org/pypy/pypy/changeset/0d1dc4ba30d3/ Log:trace versioning now compiles each version just once, and attaches patches all further guards to the bridge

[pypy-commit] pypy vecopt: rpython hint, attach_bridge is now called stitch_bridge

Author: Richard Plangger r...@pasra.at Branch: vecopt Changeset: r78585:6b68821bc6e3 Date: 2015-07-17 17:30 +0200 http://bitbucket.org/pypy/pypy/changeset/6b68821bc6e3/ Log:rpython hint, attach_bridge is now called stitch_bridge diff --git a/rpython/jit/backend/llsupport/assembler.py

[pypy-commit] pypy vecopt: inserting guard early exit in user traces if the config turns on these setting

Author: Richard Plangger r...@pasra.at Branch: vecopt Changeset: r78554:5190e9b953e7 Date: 2015-07-14 16:07 +0200 http://bitbucket.org/pypy/pypy/changeset/5190e9b953e7/ Log:inserting guard early exit in user traces if the config turns on these setting diff --git

[pypy-commit] pypy vecopt: added ABC optimization that is turned on when executed when user code is vectorized

Author: Richard Plangger r...@pasra.at Branch: vecopt Changeset: r78558:04f489dd60dd Date: 2015-07-16 12:16 +0200 http://bitbucket.org/pypy/pypy/changeset/04f489dd60dd/ Log:added ABC optimization that is turned on when executed when user code is vectorized note that this optimization

[pypy-commit] pypy vecopt: rpython hints, saving the loop version the compileloopversion descr

Author: Richard Plangger r...@pasra.at Branch: vecopt Changeset: r78559:841f77615665 Date: 2015-07-16 16:06 +0200 http://bitbucket.org/pypy/pypy/changeset/841f77615665/ Log:rpython hints, saving the loop version the compileloopversion descr diff --git a/rpython/jit/backend/x86/assembler.py

[pypy-commit] pypy vecopt: rewriting parts of the guard strength reduction to eliminate array bound checks

Author: Richard Plangger r...@pasra.at Branch: vecopt Changeset: r78555:961725ecb559 Date: 2015-07-15 17:32 +0200 http://bitbucket.org/pypy/pypy/changeset/961725ecb559/ Log:rewriting parts of the guard strength reduction to eliminate array bound checks diff --git

[pypy-commit] pypy s390x-backend: testing several other values for floating point addition

Author: Richard Plangger Branch: s390x-backend Changeset: r80388:8367c6c91fdf Date: 2015-10-22 14:16 +0200 http://bitbucket.org/pypy/pypy/changeset/8367c6c91fdf/ Log:testing several other values for floating point addition diff --git

[pypy-commit] pypy s390x-backend: allocated memory, and stored float result into it, correctly read it afterwards

Author: Richard Plangger Branch: s390x-backend Changeset: r80387:ec9e69c4ffde Date: 2015-10-22 13:20 +0200 http://bitbucket.org/pypy/pypy/changeset/ec9e69c4ffde/ Log:allocated memory, and stored float result into it, correctly read it afterwards diff --git

[pypy-commit] pypy s390x-backend: syscall write working properly. string put into literal pool

Author: Richard Plangger Branch: s390x-backend Changeset: r80380:6ad3bdfddaa3 Date: 2015-10-21 14:42 +0200 http://bitbucket.org/pypy/pypy/changeset/6ad3bdfddaa3/ Log:syscall write working properly. string put into literal pool diff --git

[pypy-commit] pypy s390x-backend: testing floating point operations, load float and round it to integer

Author: Richard Plangger Branch: s390x-backend Changeset: r80385:05b9b0babd4d Date: 2015-10-22 11:40 +0200 http://bitbucket.org/pypy/pypy/changeset/05b9b0babd4d/ Log:testing floating point operations, load float and round it to integer diff --git

[pypy-commit] pypy s390x-backend: made the instruction type RRF more general to support each unsupported parameter

Author: Richard Plangger Branch: s390x-backend Changeset: r80386:535d3fb38323 Date: 2015-10-22 12:13 +0200 http://bitbucket.org/pypy/pypy/changeset/535d3fb38323/ Log:made the instruction type RRF more general to support each unsupported parameter diff --git

[pypy-commit] pypy s390x-backend: floating point comparison operations

Author: Richard Plangger Branch: s390x-backend Changeset: r80397:6f08bc334a9b Date: 2015-10-22 16:15 +0200 http://bitbucket.org/pypy/pypy/changeset/6f08bc334a9b/ Log:floating point comparison operations diff --git a/rpython/jit/backend/zarch/instructions.py

[pypy-commit] pypy s390x-backend: testing single float to float cast, testing int64 to float cast, added div (with remainer) instr

Author: Richard Plangger Branch: s390x-backend Changeset: r80395:20f482e7b1ef Date: 2015-10-22 16:01 +0200 http://bitbucket.org/pypy/pypy/changeset/20f482e7b1ef/ Log:testing single float to float cast, testing int64 to float cast, added div (with remainer) instr

[pypy-commit] pypy s390x-backend: instrs float division

Author: Richard Plangger Branch: s390x-backend Changeset: r80394:70f5409c0a1c Date: 2015-10-22 15:19 +0200 http://bitbucket.org/pypy/pypy/changeset/70f5409c0a1c/ Log:instrs float division diff --git a/rpython/jit/backend/zarch/instructions.py

[pypy-commit] pypy s390x-backend: adding and adjusting structure while processing through assemble_loop method

Author: Richard Plangger Branch: s390x-backend Changeset: r80459:c877ffac4111 Date: 2015-10-26 11:52 +0100 http://bitbucket.org/pypy/pypy/changeset/c877ffac4111/ Log:adding and adjusting structure while processing through assemble_loop method diff --git

[pypy-commit] pypy s390x-backend: more skeleton structure

Author: Richard Plangger Branch: s390x-backend Changeset: r80458:b0d5eccd58d1 Date: 2015-10-26 09:56 +0100 http://bitbucket.org/pypy/pypy/changeset/b0d5eccd58d1/ Log:more skeleton structure diff --git a/rpython/jit/backend/zarch/helper/__init__.py

[pypy-commit] pypy s390x-backend: added docu for the backend. described the missing libffi-devel on redhat linux 6.5 and how to install it manually

Author: Richard Plangger Branch: s390x-backend Changeset: r80457:9a86a04617d8 Date: 2015-10-26 09:56 +0100 http://bitbucket.org/pypy/pypy/changeset/9a86a04617d8/ Log:added docu for the backend. described the missing libffi-devel on redhat linux 6.5 and how to

[pypy-commit] pypy s390x-backend: copy copy copy. adding the skeleton structure for the assembler, regalloc and various other modules needed for assembly

Author: Richard Plangger Branch: s390x-backend Changeset: r80456:2fc81cd2ea51 Date: 2015-10-26 09:49 +0100 http://bitbucket.org/pypy/pypy/changeset/2fc81cd2ea51/ Log:copy copy copy. adding the skeleton structure for the assembler, regalloc and various other

[pypy-commit] pypy s390x-backend: adapted some arch details, added failure recovery, finish resop (partly)

Author: Richard Plangger Branch: s390x-backend Changeset: r80466:85a292e8a0ad Date: 2015-10-27 11:20 +0100 http://bitbucket.org/pypy/pypy/changeset/85a292e8a0ad/ Log:adapted some arch details, added failure recovery, finish resop (partly) diff --git

[pypy-commit] pypy s390x-backend: towards a correct guard_quick_failure

Author: Richard Plangger Branch: s390x-backend Changeset: r80473:2c01ef6261a8 Date: 2015-10-28 16:03 +0100 http://bitbucket.org/pypy/pypy/changeset/2c01ef6261a8/ Log:towards a correct guard_quick_failure diff --git a/rpython/jit/backend/zarch/assembler.py

[pypy-commit] pypy s390x-backend: correctly jumping out of the program after guard failure, but there is something wrong with the saving to the dead frame

Author: Richard Plangger Branch: s390x-backend Changeset: r80481:b39bf57b3e2f Date: 2015-10-29 16:18 +0100 http://bitbucket.org/pypy/pypy/changeset/b39bf57b3e2f/ Log:correctly jumping out of the program after guard failure, but there is something wrong with the

[pypy-commit] pypy s390x-backend: added floating point operations (add, sub, mul, div) as resoperation, added first version of the literal pool prepended to the assembler piece

Author: Richard Plangger Branch: s390x-backend Changeset: r80467:768bbe0e9944 Date: 2015-10-27 17:01 +0100 http://bitbucket.org/pypy/pypy/changeset/768bbe0e9944/ Log:added floating point operations (add,sub,mul,div) as resoperation, added first version of the

[pypy-commit] pypy s390x-backend: literal/constant pool correctly assembled, float test (linear float loop) passing

Author: Richard Plangger Branch: s390x-backend Changeset: r80468:ab25d19c932c Date: 2015-10-27 17:12 +0100 http://bitbucket.org/pypy/pypy/changeset/ab25d19c932c/ Log:literal/constant pool correctly assembled, float test (linear float loop) passing diff --git

[pypy-commit] pypy s390x-backend: many more methods in place. it is now possible to step through the whole assemble_loop method for a trace with like int_add(...), finish(...). sadly the code is not y

Author: Richard Plangger Branch: s390x-backend Changeset: r80464:bc3119a598cf Date: 2015-10-26 15:38 +0100 http://bitbucket.org/pypy/pypy/changeset/bc3119a598cf/ Log:many more methods in place. it is now possible to step through the whole assemble_loop method for

[pypy-commit] pypy s390x-backend: catchup with default

Author: Richard Plangger Branch: s390x-backend Changeset: r80381:a239179e43b6 Date: 2015-10-21 15:02 +0200 http://bitbucket.org/pypy/pypy/changeset/a239179e43b6/ Log:catchup with default diff too long, truncating to 2000 out of 27093 lines diff --git a/.gitignore

[pypy-commit] pypy s390x-backend: assembler recursion: testing if it the assembler can correctly invoke a recursive function. added helper functions to label positions (in the test suite)

Author: Richard Plangger Branch: s390x-backend Changeset: r80377:aa2a464734d2 Date: 2015-10-21 13:58 +0200 http://bitbucket.org/pypy/pypy/changeset/aa2a464734d2/ Log:assembler recursion: testing if it the assembler can correctly invoke a recursive function. added

[pypy-commit] pypy s390x-backend: adding resoperations to regalloc/assembler (label, int_(lt, eq, ...), guards)

Author: Richard Plangger Branch: s390x-backend Changeset: r80471:3a2cb683d03e Date: 2015-10-28 10:11 +0100 http://bitbucket.org/pypy/pypy/changeset/3a2cb683d03e/ Log:adding resoperations to regalloc/assembler (label,int_(lt,eq,...), guards) diff --git

[pypy-commit] pypy s390x-backend: adding jump instruction and working on correct assembly of guard failure

Author: Richard Plangger Branch: s390x-backend Changeset: r80472:dd415ed2de42 Date: 2015-10-28 12:01 +0100 http://bitbucket.org/pypy/pypy/changeset/dd415ed2de42/ Log:adding jump instruction and working on correct assembly of guard failure diff --git

[pypy-commit] pypy py3.3: pseudo fix of this test, I would remove it. maybe someone wants to review this test?

Author: Richard Plangger Branch: py3.3 Changeset: r80635:14fcbf845d84 Date: 2015-11-05 17:49 +0100 http://bitbucket.org/pypy/pypy/changeset/14fcbf845d84/ Log:pseudo fix of this test, I would remove it. maybe someone wants to review this test? diff --git

[pypy-commit] pypy s390x-backend: label now loads the constant pool when it is entered. the jump back within the same loop (peeled loop does not reload the literal pool, because it is not changed)

Author: Richard Plangger Branch: s390x-backend Changeset: r80631:45f50d672a78 Date: 2015-11-09 12:07 +0100 http://bitbucket.org/pypy/pypy/changeset/45f50d672a78/ Log:label now loads the constant pool when it is entered. the jump back within the same loop (peeled

[pypy-commit] pypy s390x-backend: freed r12 of its burden as a base pointer, saving the pool address (it is known when jumping to a label) to the bridge pool instead of on the stack

Author: Richard Plangger Branch: s390x-backend Changeset: r80630:a45f6bccf61b Date: 2015-11-05 11:27 +0100 http://bitbucket.org/pypy/pypy/changeset/a45f6bccf61b/ Log:freed r12 of its burden as a base pointer, saving the pool address (it is known when jumping to a

[pypy-commit] pypy s390x-backend: logical division for ufloor_div, added some methods for to get two registers next to each other from the reg alloc (not yet complete)

Author: Richard Plangger Branch: s390x-backend Changeset: r80633:6db64d28c955 Date: 2015-11-11 13:08 +0100 http://bitbucket.org/pypy/pypy/changeset/6db64d28c955/ Log:logical division for ufloor_div, added some methods for to get two registers next to each other

[pypy-commit] pypy s390x-backend: added division opcode, multiply opcode, int32 imm add and sub, started to implement int_mul, int_div.

Author: Richard Plangger Branch: s390x-backend Changeset: r80632:f7d3b4343ec7 Date: 2015-11-11 10:40 +0100 http://bitbucket.org/pypy/pypy/changeset/f7d3b4343ec7/ Log:added division opcode, multiply opcode, int32 imm add and sub, started to implement int_mul,

[pypy-commit] pypy s390x-backend: implemented int_mul, int_floordiv, uint_floordiv and int_mod

Author: Richard Plangger Branch: s390x-backend Changeset: r80634:5a93f832d42a Date: 2015-11-11 15:46 +0100 http://bitbucket.org/pypy/pypy/changeset/5a93f832d42a/ Log:implemented int_mul, int_floordiv, uint_floordiv and int_mod added test case to ensure the

[pypy-commit] pypy s390x-backend: added regalloc/assembler for shift & logic operations, tested them in a very basic trace

Author: Richard Plangger Branch: s390x-backend Changeset: r80646:ec0e146d57f6 Date: 2015-11-12 13:41 +0100 http://bitbucket.org/pypy/pypy/changeset/ec0e146d57f6/ Log:added regalloc/assembler for shift & logic operations, tested them in a very basic trace diff

[pypy-commit] pypy s390x-backend: added helper to prepare regalloc for an unary value, added load positive and load negative instruction

Author: Richard Plangger Branch: s390x-backend Changeset: r80647:56dc6a5d2a55 Date: 2015-11-12 14:33 +0100 http://bitbucket.org/pypy/pypy/changeset/56dc6a5d2a55/ Log:added helper to prepare regalloc for an unary value, added load positive and load negative

[pypy-commit] pypy s390x-backend: added test for an overflow operations, added regalloc for guards (overflow, exception). they are not yet fully functional

Author: Richard Plangger Branch: s390x-backend Changeset: r80661:d49e13685df3 Date: 2015-11-13 12:52 +0100 http://bitbucket.org/pypy/pypy/changeset/d49e13685df3/ Log:added test for an overflow operations, added regalloc for guards (overflow, exception). they are

[pypy-commit] pypy s390x-backend: completed implementation for int_is_true, int_is_zero. added flush_cc method and fixed the LARL problem (test suite provided wrong number to gnu asm)

Author: Richard Plangger Branch: s390x-backend Changeset: r80655:7e4f29d5c048 Date: 2015-11-13 10:18 +0100 http://bitbucket.org/pypy/pypy/changeset/7e4f29d5c048/ Log:completed implementation for int_is_true, int_is_zero. added flush_cc method and fixed the LARL

[pypy-commit] pypy s390x-backend: guard overflow is behaving properly for int_add_ovf/int_sub_ovf

Author: Richard Plangger Branch: s390x-backend Changeset: r80701:f2281bea8745 Date: 2015-11-16 08:56 +0100 http://bitbucket.org/pypy/pypy/changeset/f2281bea8745/ Log:guard overflow is behaving properly for int_add_ovf/int_sub_ovf diff --git

[pypy-commit] pypy s390x-backend: added regalloc/assembler for int_neg, int_invert

Author: Richard Plangger Branch: s390x-backend Changeset: r80650:54d56775dc1e Date: 2015-11-12 19:54 +0100 http://bitbucket.org/pypy/pypy/changeset/54d56775dc1e/ Log:added regalloc/assembler for int_neg, int_invert diff --git

[pypy-commit] pypy s390x-backend: added test to stress register pair allocation (even odd) as it is needed for division, some invariant is failing still

Author: Richard Plangger Branch: s390x-backend Changeset: r80729:5df254e363c4 Date: 2015-11-17 11:41 +0100 http://bitbucket.org/pypy/pypy/changeset/5df254e363c4/ Log:added test to stress register pair allocation (even odd) as it is needed for division, some

[pypy-commit] pypy s390x-backend: finished implementation to allocate a register pair (even/odd), added test case to ensure the spilling is done correctly

Author: Richard Plangger Branch: s390x-backend Changeset: r80730:0b2023218277 Date: 2015-11-17 14:37 +0100 http://bitbucket.org/pypy/pypy/changeset/0b2023218277/ Log:finished implementation to allocate a register pair (even/odd), added test case to ensure the

[pypy-commit] pypy s390x-backend: ironed out the bug in mul overflow, test runner is now passing two ovf tests!

Author: Richard Plangger Branch: s390x-backend Changeset: r80732:173b585af649 Date: 2015-11-17 20:00 +0100 http://bitbucket.org/pypy/pypy/changeset/173b585af649/ Log:ironed out the bug in mul overflow, test runner is now passing two ovf tests! diff --git

[pypy-commit] pypy s390x-backend: test drag along, found one bug (did not copy compare long instr bytes from manual)

Author: Richard Plangger Branch: s390x-backend Changeset: r80515:4baab7a89095 Date: 2015-11-03 16:04 +0100 http://bitbucket.org/pypy/pypy/changeset/4baab7a89095/ Log:test drag along, found one bug (did not copy compare long instr bytes from manual) diff --git

[pypy-commit] pypy s390x-backend: saving byte_count as attribute to codebuilder instead as attribute of the function

Author: Richard Plangger Branch: s390x-backend Changeset: r80511:e9d5e097f0aa Date: 2015-11-02 18:21 +0100 http://bitbucket.org/pypy/pypy/changeset/e9d5e097f0aa/ Log:saving byte_count as attribute to codebuilder instead as attribute of the function diff --git

[pypy-commit] pypy s390x-backend: ironed out issues that took the wrong register. excluding the scratch register from managed ones and correctly setting the registers on the cpu now gives the desired

Author: Richard Plangger Branch: s390x-backend Changeset: r80536:78a1e03178a0 Date: 2015-11-04 13:43 +0100 http://bitbucket.org/pypy/pypy/changeset/78a1e03178a0/ Log:ironed out issues that took the wrong register. excluding the scratch register from managed ones

[pypy-commit] pypy s390x-backend: reordered free registers and force result in register (wrong order double loaded values already in a register)

Author: Richard Plangger Branch: s390x-backend Changeset: r80537:094ee6d25c63 Date: 2015-11-04 14:20 +0100 http://bitbucket.org/pypy/pypy/changeset/094ee6d25c63/ Log:reordered free registers and force result in register (wrong order double loaded values already

[pypy-commit] pypy s390x-backend: first loop correctly assembled. it is correctly entered, correctly calulating the counter variable and cleanly exiting back to the VM

Author: Richard Plangger Branch: s390x-backend Changeset: r80497:6fbf6c1ae931 Date: 2015-11-02 10:43 +0100 http://bitbucket.org/pypy/pypy/changeset/6fbf6c1ae931/ Log:first loop correctly assembled. it is correctly entered, correctly calulating the counter

[pypy-commit] pypy s390x-backend: adding trap2 instruction, skeletal structure to assemble a bridge, allocating additional space in pool if a 64bit jump is needed (e.g. bridge jump to loop token of al

Author: Richard Plangger Branch: s390x-backend Changeset: r80499:468121ce68fa Date: 2015-11-02 12:25 +0100 http://bitbucket.org/pypy/pypy/changeset/468121ce68fa/ Log:adding trap2 instruction, skeletal structure to assemble a bridge, allocating additional space in

[pypy-commit] pypy py3.3: need to write size (32 bits) just after timestamp

Author: Richard Plangger Branch: py3.3 Changeset: r80548:c389c7b3f1ae Date: 2015-11-05 16:25 +0100 http://bitbucket.org/pypy/pypy/changeset/c389c7b3f1ae/ Log:need to write size (32 bits) just after timestamp diff --git a/pypy/module/imp/test/test_app.py

[pypy-commit] pypy py3.3: self.ext... was not enough, access the module _imp stored in self.imp instead

Author: Richard Plangger Branch: py3.3 Changeset: r80547:b22b2972eec4 Date: 2015-11-05 15:36 +0100 http://bitbucket.org/pypy/pypy/changeset/b22b2972eec4/ Log:self.ext... was not enough, access the module _imp stored in self.imp instead diff --git

[pypy-commit] pypy s390x-backend: jump to loop header from a bridge is now correctly working

Author: Richard Plangger Branch: s390x-backend Changeset: r80514:07e92acaeeec Date: 2015-11-03 15:23 +0100 http://bitbucket.org/pypy/pypy/changeset/07e92acaeeec/ Log:jump to loop header from a bridge is now correctly working diff --git

[pypy-commit] pypy s390x-backend: saving the last used constant pool below the stack pointer

Author: Richard Plangger Branch: s390x-backend Changeset: r80516:2e5796108f90 Date: 2015-11-03 17:50 +0100 http://bitbucket.org/pypy/pypy/changeset/2e5796108f90/ Log:saving the last used constant pool below the stack pointer diff --git

[pypy-commit] pypy vecopt-merge: promoted value size added to expected trace (as a guard_value)

Author: Richard Plangger Branch: vecopt-merge Changeset: r80205:e8a7239d1430 Date: 2015-10-14 16:54 +0200 http://bitbucket.org/pypy/pypy/changeset/e8a7239d1430/ Log:promoted value size added to expected trace (as a guard_value) diff --git

[pypy-commit] pypy s390x-backend: copied locations and added gp registers (as well as floating register)

Author: Richard Plangger Branch: s390x-backend Changeset: r80210:7881dc958ddb Date: 2015-10-14 17:18 +0200 http://bitbucket.org/pypy/pypy/changeset/7881dc958ddb/ Log:copied locations and added gp registers (as well as floating register) diff --git

[pypy-commit] pypy vecopt-merge: skipping test_zjit for a non vectorizing cpu, all of the tests expect a SIMD backend to be implemented

Author: Richard Plangger Branch: vecopt-merge Changeset: r80209:ef76f6b37cda Date: 2015-10-14 16:59 +0200 http://bitbucket.org/pypy/pypy/changeset/ef76f6b37cda/ Log:skipping test_zjit for a non vectorizing cpu, all of the tests expect a SIMD backend to be

[pypy-commit] pypy s390x-backend: added more assembler functions (branching, loading, ...) and added first small test that assembles a real assembler block and executes it

Author: Richard Plangger Branch: s390x-backend Changeset: r80334:7dae60560404 Date: 2015-10-19 11:07 +0200 http://bitbucket.org/pypy/pypy/changeset/7dae60560404/ Log:added more assembler functions (branching, loading, ...) and added first small test that

[pypy-commit] pypy s390x-backend: called first subroutine in assembler

Author: Richard Plangger Branch: s390x-backend Changeset: r80335:2b4c4bd98951 Date: 2015-10-19 15:29 +0200 http://bitbucket.org/pypy/pypy/changeset/2b4c4bd98951/ Log:called first subroutine in assembler diff --git a/rpython/jit/backend/zarch/assembler.py

[pypy-commit] pypy s390x-backend: first loop (that includes a branching instruction on condition), substract and register move added to instructions

Author: Richard Plangger Branch: s390x-backend Changeset: r80336:cff394b2f479 Date: 2015-10-19 16:42 +0200 http://bitbucket.org/pypy/pypy/changeset/cff394b2f479/ Log:first loop (that includes a branching instruction on condition), substract and register move

[pypy-commit] pypy default: merged vecopt

Author: Richard Plangger Branch: Changeset: r80235:4a3dc93c017c Date: 2015-10-15 14:35 +0200 http://bitbucket.org/pypy/pypy/changeset/4a3dc93c017c/ Log:merged vecopt diff too long, truncating to 2000 out of 14247 lines diff --git a/.gitignore b/.gitignore ---

[pypy-commit] pypy s390x-backend: register immediate encoding

Author: Richard Plangger Branch: s390x-backend Changeset: r80232:066bb29ef362 Date: 2015-10-15 12:16 +0200 http://bitbucket.org/pypy/pypy/changeset/066bb29ef362/ Log:register immediate encoding diff --git a/rpython/jit/backend/zarch/codebuilder.py

[pypy-commit] pypy s390x-backend: immediate encoding with base register displacement (SI)

Author: Richard Plangger Branch: s390x-backend Changeset: r80234:235a94b23040 Date: 2015-10-15 14:33 +0200 http://bitbucket.org/pypy/pypy/changeset/235a94b23040/ Log:immediate encoding with base register displacement (SI) diff --git

[pypy-commit] pypy vecopt-merge: close branch

Author: Richard Plangger Branch: vecopt-merge Changeset: r80236:e040414ce026 Date: 2015-10-15 14:36 +0200 http://bitbucket.org/pypy/pypy/changeset/e040414ce026/ Log:close branch ___ pypy-commit mailing list

[pypy-commit] pypy vecopt: close branch

Author: Richard Plangger Branch: vecopt Changeset: r80237:5548644da690 Date: 2015-10-15 14:36 +0200 http://bitbucket.org/pypy/pypy/changeset/5548644da690/ Log:close branch ___ pypy-commit mailing list pypy-commit@python.org

[pypy-commit] pypy s390x-backend: index base displace with a long displacement (20 bits instead of 12)

Author: Richard Plangger Branch: s390x-backend Changeset: r80231:c919b5688d2b Date: 2015-10-15 11:54 +0200 http://bitbucket.org/pypy/pypy/changeset/c919b5688d2b/ Log:index base displace with a long displacement (20 bits instead of 12) diff --git

[pypy-commit] pypy vecopt-merge: merged default

Author: Richard Plangger Branch: vecopt-merge Changeset: r80229:04ab6b2dc6ff Date: 2015-10-15 09:33 +0200 http://bitbucket.org/pypy/pypy/changeset/04ab6b2dc6ff/ Log:merged default diff too long, truncating to 2000 out of 2228 lines diff --git

[pypy-commit] pypy s390x-backend: index base displace parameter implemented

Author: Richard Plangger Branch: s390x-backend Changeset: r80230:99988dacdae0 Date: 2015-10-15 11:31 +0200 http://bitbucket.org/pypy/pypy/changeset/99988dacdae0/ Log:index base displace parameter implemented diff --git a/rpython/jit/backend/zarch/codebuilder.py

[pypy-commit] pypy s390x-backend: extending to the different opcode formats, now supporting agr the 64 bit version of signed integer add!

Author: Richard Plangger Branch: s390x-backend Changeset: r80214:b21ba89abdb2 Date: 2015-10-14 19:01 +0200 http://bitbucket.org/pypy/pypy/changeset/b21ba89abdb2/ Log:extending to the different opcode formats, now supporting agr the 64 bit version of signed

[pypy-commit] pypy vecopt-merge: removed fromfloat call, but called constructor (wrong), fixed

Author: Richard Plangger Branch: vecopt-merge Changeset: r80189:7c83ce701286 Date: 2015-10-14 08:52 +0200 http://bitbucket.org/pypy/pypy/changeset/7c83ce701286/ Log:removed fromfloat call, but called constructor (wrong), fixed diff --git a/rpython/jit/tool/oparser.py

[pypy-commit] pypy vecopt-merge: test case reduced size of constant integer to pass this test

Author: Richard Plangger Branch: vecopt-merge Changeset: r80190:1c315f467e89 Date: 2015-10-14 08:55 +0200 http://bitbucket.org/pypy/pypy/changeset/1c315f467e89/ Log:test case reduced size of constant integer to pass this test diff --git

[pypy-commit] pypy s390x-backend: copy copy copy. insertion of dummy methods to get the test environment going

Author: Richard Plangger Branch: s390x-backend Changeset: r80194:1c30732c9462 Date: 2015-10-14 09:56 +0200 http://bitbucket.org/pypy/pypy/changeset/1c30732c9462/ Log:copy copy copy. insertion of dummy methods to get the test environment going diff --git

[pypy-commit] pypy s390x-backend: added base displacement parameters with length in various flavours (instr category named ss_a, ss_b, ss_c)

Author: Richard Plangger Branch: s390x-backend Changeset: r80239:d28ca84c9d6a Date: 2015-10-15 16:55 +0200 http://bitbucket.org/pypy/pypy/changeset/d28ca84c9d6a/ Log:added base displacement parameters with length in various flavours (instr category named ss_a,

[pypy-commit] pypy s390x-backend: SIY extended 20 bit base displacement encoding

Author: Richard Plangger Branch: s390x-backend Changeset: r80238:96207b27efbe Date: 2015-10-15 15:13 +0200 http://bitbucket.org/pypy/pypy/changeset/96207b27efbe/ Log:SIY extended 20 bit base displacement encoding diff --git a/rpython/jit/backend/zarch/codebuilder.py

[pypy-commit] pypy s390x-backend: started the auto instruction encoding, AR_rr correctly assembles

Author: Richard Plangger Branch: s390x-backend Changeset: r80195:6177697cbd11 Date: 2015-10-14 12:25 +0200 http://bitbucket.org/pypy/pypy/changeset/6177697cbd11/ Log:started the auto instruction encoding, AR_rr correctly assembles diff --git

[pypy-commit] pypy vecopt-merge: merged default

Author: Richard Plangger Branch: vecopt-merge Changeset: r80036:598c56268e90 Date: 2015-10-08 08:59 +0200 http://bitbucket.org/pypy/pypy/changeset/598c56268e90/ Log:merged default diff too long, truncating to 2000 out of 6822 lines diff --git a/dotviewer/graphclient.py

[pypy-commit] pypy vecopt-merge: quick fix for the guard exit, the first argument is unpacked, added a test to check if this leads to a wrong result

Author: Richard Plangger Branch: vecopt-merge Changeset: r80037:68cd8c5a751e Date: 2015-10-08 10:11 +0200 http://bitbucket.org/pypy/pypy/changeset/68cd8c5a751e/ Log:quick fix for the guard exit, the first argument is unpacked, added a test to check if this leads

<    1   2   3   4   5   6   7   8   9   10   >