I'm trying to extract module contents from Verilog, which has the form
of;
module foo (port1, port2, ... );
// module contents to extract here.
...
endmodule
To extract the module contents, I'm planning to do something like;
from pyparsing import *
ident =
Inyeol Lee [EMAIL PROTECTED] wrote in message
news:[EMAIL PROTECTED]
I'm trying to extract module contents from Verilog, which has the form
of;
module foo (port1, port2, ... );
// module contents to extract here.
...
endmodule
To extract the module contents, I'm
On Mon, Nov 28, 2005 at 09:00:58PM +, Paul McGuire wrote:
Inyeol Lee [EMAIL PROTECTED] wrote in message
[...]
How should I write the part of 'module_contents'? It's an arbitrary text
which doesn't contain 'endmodule' keyword. I don't want to use full
scale Verilog parser for this task.
