Re: Python for System Verilog testbench

On 9/14/18 11:41 AM, Bobby wrote: Hi George WOW! thanks for the reply and specially thanks for using the word 'BDD'. I read the articles regarding BDD the whole day and understood the concepts. Now will get this Pytest test framework with pytest bdd plugin. I found out it follows this Gherkin s

Re: Python for System Verilog testbench

Hi George WOW! thanks for the reply and specially thanks for using the word 'BDD'. I read the articles regarding BDD the whole day and understood the concepts. Now will get this Pytest test framework with pytest bdd plugin. I found out it follows this Gherkin syntax. Then I read about this Gherki

Re: Python for System Verilog testbench

Bobby ezt írta (időpont: 2018. szept. 14., P 0:16): > > I have a very simple System Verilog (SV) adder as my DUT (device under > test). I would like to generate a test bench for this DUT based on the > 'requirements'. I wrote its (DUT) functions in simple text as > 'requirements' while followin

Python for System Verilog testbench

I have a very simple System Verilog (SV) adder as my DUT (device under test). I would like to generate a test bench for this DUT based on the 'requirements'. I wrote its (DUT) functions in simple text as 'requirements' while following a particular syntax. Now through the help of grammar, I