Re: [PULL 00/17] Block layer patches

On Fri, 18 Dec 2020 at 12:10, Kevin Wolf wrote: > > The following changes since commit 75ee62ac606bfc9eb59310b9446df3434bf6e8c2: > > Merge remote-tracking branch > 'remotes/ehabkost-gl/tags/x86-next-pull-request' into staging (2020-12-17 > 18:53:36 +) > > are available in the Git

[PATCH 22/22] docs/system: riscv: Add documentation for sifive_u machine

From: Bin Meng This adds detailed documentation for RISC-V `sifive_u` machine, including the following information: - Supported devices - Hardware configuration information - Boot options - Machine-specific options - Running Linux kernel - Running VxWorks kernel - Running U-Boot, and with an

[PATCH 17/22] hw/riscv: sifive_u: Add QSPI0 controller and connect a flash

From: Bin Meng This adds the QSPI0 controller to the SoC, and connnects an ISSI 25WP256 flash to it. The generation of corresponding device tree source fragment is also added. With this commit, upstream U-Boot for the SiFive HiFive Unleashed board can boot on QEMU 'sifive_u' out of the box.

[PATCH 18/22] hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card

From: Bin Meng This adds the QSPI2 controller to the SoC, and connnects an SD card to it. The generation of corresponding device tree source fragment is also added. Specify machine property `msel` to 11 to boot the same upstream U-Boot SPL and payload image for the SiFive HiFive Unleashed

[PATCH 19/22] hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value

From: Bin Meng All other peripherals' IRQs are in the format of decimal value. Change SIFIVE_U_GEM_IRQ to be consistent. Signed-off-by: Bin Meng --- include/hw/riscv/sifive_u.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/hw/riscv/sifive_u.h

[PATCH 16/22] hw/ssi: Add SiFive SPI controller support

From: Bin Meng This adds the SiFive SPI controller model for the FU540 SoC. The direct memory-mapped SPI flash mode is unsupported. Signed-off-by: Bin Meng --- include/hw/ssi/sifive_spi.h | 47 ++ hw/ssi/sifive_spi.c | 290 hw/ssi/Kconfig

[PATCH 21/22] docs/system: Add RISC-V documentation

From: Bin Meng Add RISC-V system emulator documentation for generic information. `Board-specific documentation` and `RISC-V CPU features` are only a placeholder and will be added in the future. Signed-off-by: Bin Meng --- docs/system/target-riscv.rst | 62

[PATCH 15/22] hw/sd: ssi-sd: Support multiple block write

From: Bin Meng For a multiple block write operation, each block begins with a multi write start token. Unlike the SD mode that the multiple block write ends when receiving a STOP_TRAN command (CMD12), a special stop tran tocken is used to signal the card. Emulating this by manually sending a

[PATCH 12/22] hw/sd: sd.h: Cosmetic change of using spaces

From: Bin Meng QEMU conding convention prefers spaces over tabs. Signed-off-by: Bin Meng --- include/hw/sd/sd.h | 42 +- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/include/hw/sd/sd.h b/include/hw/sd/sd.h index

[PATCH 20/22] docs/system: Sort targets in alphabetical order

From: Bin Meng Signed-off-by: Bin Meng --- docs/system/targets.rst | 19 --- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/docs/system/targets.rst b/docs/system/targets.rst index 560783644d..564cea9a9b 100644 --- a/docs/system/targets.rst +++

[PATCH 10/22] hw/sd: sd: Remove duplicated codes in single/multiple block read/write

From: Bin Meng The single block read (CMD17) codes are the same as the multiple block read (CMD18). Merge them into one. The same applies to single block write (CMD24) and multiple block write (CMD25). Signed-off-by: Bin Meng --- hw/sd/sd.c | 47

[PATCH 14/22] hw/sd: ssi-sd: Support single block write

From: Bin Meng Add 2 more states for the block write operation. The SPI host needs to send a data start tocken to start the transfer, and the data block written to the card will be acknowledged by a data response tocken. Signed-off-by: Bin Meng --- hw/sd/ssi-sd.c | 37

[PATCH 11/22] hw/sd: sd: Allow single/multiple block write for SPI mode

From: Bin Meng At present the single/multiple block write in SPI mode is blocked by sd_normal_command(). Remove the limitation. Signed-off-by: Bin Meng --- hw/sd/sd.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/hw/sd/sd.c b/hw/sd/sd.c index 1ada616e1e..67e5f7c05d 100644 ---

[PATCH 09/22] hw/sd: ssi-sd: Use macros for the dummy value and tokens in the transfer

From: Bin Meng At present the codes use hardcoded numbers (0xff/0xfe) for the dummy value and block start token. Replace them with macros, and add more tokens for multiple block write. Signed-off-by: Bin Meng --- hw/sd/ssi-sd.c | 30 +- 1 file changed, 21

[PATCH 05/22] hw/sd: sd: Drop sd_crc16()

From: Bin Meng commit f6fb1f9b319f ("sdcard: Correct CRC16 offset in sd_function_switch()") changed the 16-bit CRC to be stored at offset 64. In fact, this CRC calculation is completely wrong. From the original codes, it wants to calculate the CRC16 of the first 64 bytes of sd->data[], however

[PATCH 03/22] hw/sd: ssi-sd: Fix incorrect card response sequence

From: Bin Meng Per the "Physical Layer Specification Version 8.00" chapter 7.5.1, "Command/Response", there is a minimum 8 clock cycles (Ncr) before the card response shows up on the data out line. However current implementation jumps directly to the sending response state after all 6 bytes

[PATCH 04/22] hw/sd: sd: Support CMD59 for SPI mode

From: Bin Meng After the card is put into SPI mode, CRC check for all commands including CMD0 will be done according to CMD59 setting. But this command is currently unimplemented. Simply allow the decoding of CMD59, but the CRC check is still ignored. Signed-off-by: Bin Meng --- hw/sd/sd.c |

[PATCH 13/22] hw/sd: Introduce receive_ready() callback

From: Bin Meng At present there is a data_ready() callback for the SD data read path. Let's add a receive_ready() for the SD data write path. Signed-off-by: Bin Meng --- include/hw/sd/sd.h | 2 ++ hw/sd/core.c | 13 + hw/sd/sd.c | 6 ++ 3 files changed, 21

[PATCH 08/22] hw/sd: ssi-sd: Support multiple block read (CMD18)

From: Bin Meng In the case of a multiple block read operation every transfered block has its suffix of CRC16. Update the state machine logic to handle multiple block read. This also fixed the wrong command index for STOP_TRANSMISSION, the required command to interupt the multiple block read

[PATCH 07/22] hw/sd: ssi-sd: Suffix a data block with CRC16

From: Bin Meng Per the SD spec, a valid data block is suffixed with a 16-bit CRC generated by the standard CCITT polynomial x16+x12+x5+1. This part is currently missing in the ssi-sd state machine. Without it, all data block transfer fails in guest software because the expected CRC16 is missing

[PATCH 06/22] util: Add CRC16 (CCITT) calculation routines

From: Bin Meng Import CRC16 calculation routines from Linux kernel v5.10: include/linux/crc-ccitt.h lib/crc-ccitt.c to QEMU: include/qemu/crc-ccitt.h util/crc-ccitt.c Signed-off-by: Bin Meng --- include/qemu/crc-ccitt.h | 33 ++ util/crc-ccitt.c | 127

[PATCH 01/22] hw/block: m25p80: Add ISSI SPI flash support

From: Bin Meng This adds the ISSI SPI flash support. The number of dummy cycles in fast read, fast read dual output and fast read quad output commands is currently using the default 8. Per the datasheet [1], the number of dummy cycles configurable, but this is not modeled. For flash whose size

[PATCH 00/22] hw/riscv: sifive_u: Add missing SPI support

From: Bin Meng This adds the missing SPI support to the `sifive_u` machine in the QEMU mainline. With this series, upstream U-Boot for the SiFive HiFive Unleashed board can boot on QEMU `sifive_u` out of the box. This allows users to develop and test the recommended RISC-V boot flow with a real

[PATCH 02/22] hw/block: m25p80: Add various ISSI flash information

From: Bin Meng This updates the flash information table to include various ISSI flashes that are supported by upstream U-Boot and Linux kernel. Signed-off-by: Bin Meng --- hw/block/m25p80.c | 13 + 1 file changed, 13 insertions(+) diff --git a/hw/block/m25p80.c