Re: [PATCH 17/22] hw/riscv: sifive_u: Add QSPI0 controller and connect a flash

2021-01-13 Thread Alistair Francis
On Thu, Dec 31, 2020 at 3:51 AM Bin Meng wrote: > > From: Bin Meng > > This adds the QSPI0 controller to the SoC, and connnects an ISSI > 25WP256 flash to it. The generation of corresponding device tree > source fragment is also added. > > With this commit, upstream U-Boot for the SiFive HiFive

[PATCH 17/22] hw/riscv: sifive_u: Add QSPI0 controller and connect a flash

2020-12-31 Thread Bin Meng
From: Bin Meng This adds the QSPI0 controller to the SoC, and connnects an ISSI 25WP256 flash to it. The generation of corresponding device tree source fragment is also added. With this commit, upstream U-Boot for the SiFive HiFive Unleashed board can boot on QEMU 'sifive_u' out of the box.