On Tue, Sep 06, 2022 at 10:23:57AM -0400, Michael S. Tsirkin wrote:
> On Thu, Jun 02, 2022 at 08:47:31PM +, Lev Kujawski wrote:
> > One method to enable PCI bus mastering for IDE controllers, often used
> > by x86 firmware, is to write 0x7 to the PCI command register. Neither
> > the PIIX3
Am 2. Juni 2022 20:47:31 UTC schrieb Lev Kujawski :
>One method to enable PCI bus mastering for IDE controllers, often used
>by x86 firmware, is to write 0x7 to the PCI command register. Neither
>the PIIX3 specification nor actual hardware (a Tyan S1686D system)
>permit modification of the Memory
On Thu, Jun 02, 2022 at 08:47:31PM +, Lev Kujawski wrote:
> One method to enable PCI bus mastering for IDE controllers, often used
> by x86 firmware, is to write 0x7 to the PCI command register. Neither
> the PIIX3 specification nor actual hardware (a Tyan S1686D system)
> permit modification
One method to enable PCI bus mastering for IDE controllers, often used
by x86 firmware, is to write 0x7 to the PCI command register. Neither
the PIIX3 specification nor actual hardware (a Tyan S1686D system)
permit modification of the Memory Space Enable (MSE) bit, 1, and thus
the command
