In preparation of raising -Wimplicit-fallthrough to 5, replace all fall-through comments with the fallthrough attribute pseudo-keyword.
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidiana...@linaro.org> --- target/xtensa/op_helper.c | 8 ++++---- target/xtensa/translate.c | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c index 7bb8cd6726..69b72f474d 100644 --- a/target/xtensa/op_helper.c +++ b/target/xtensa/op_helper.c @@ -73,58 +73,58 @@ void HELPER(update_ccompare)(CPUXtensaState *env, uint32_t i) /*! * Check vaddr accessibility/cache attributes and raise an exception if * specified by the ATOMCTL SR. * * Note: local memory exclusion is not implemented */ void HELPER(check_atomctl)(CPUXtensaState *env, uint32_t pc, uint32_t vaddr) { uint32_t paddr, page_size, access; uint32_t atomctl = env->sregs[ATOMCTL]; int rc = xtensa_get_physical_addr(env, true, vaddr, 1, xtensa_get_cring(env), &paddr, &page_size, &access); /* * s32c1i never causes LOAD_PROHIBITED_CAUSE exceptions, * see opcode description in the ISA */ if (rc == 0 && (access & (PAGE_READ | PAGE_WRITE)) != (PAGE_READ | PAGE_WRITE)) { rc = STORE_PROHIBITED_CAUSE; } if (rc) { HELPER(exception_cause_vaddr)(env, pc, rc, vaddr); } /* * When data cache is not configured use ATOMCTL bypass field. * See ISA, 4.3.12.4 The Atomic Operation Control Register (ATOMCTL) * under the Conditional Store Option. */ if (!xtensa_option_enabled(env->config, XTENSA_OPTION_DCACHE)) { access = PAGE_CACHE_BYPASS; } switch (access & PAGE_CACHE_MASK) { case PAGE_CACHE_WB: atomctl >>= 2; - /* fall through */ + fallthrough; case PAGE_CACHE_WT: atomctl >>= 2; - /* fall through */ + fallthrough; case PAGE_CACHE_BYPASS: if ((atomctl & 0x3) == 0) { HELPER(exception_cause_vaddr)(env, pc, LOAD_STORE_ERROR_CAUSE, vaddr); } break; case PAGE_CACHE_ISOLATE: HELPER(exception_cause_vaddr)(env, pc, LOAD_STORE_ERROR_CAUSE, vaddr); break; default: break; } } @@ -132,41 +132,41 @@ void HELPER(check_atomctl)(CPUXtensaState *env, uint32_t pc, uint32_t vaddr) void HELPER(check_exclusive)(CPUXtensaState *env, uint32_t pc, uint32_t vaddr, uint32_t is_write) { uint32_t paddr, page_size, access; uint32_t atomctl = env->sregs[ATOMCTL]; int rc = xtensa_get_physical_addr(env, true, vaddr, is_write, xtensa_get_cring(env), &paddr, &page_size, &access); if (rc) { HELPER(exception_cause_vaddr)(env, pc, rc, vaddr); } /* When data cache is not configured use ATOMCTL bypass field. */ if (!xtensa_option_enabled(env->config, XTENSA_OPTION_DCACHE)) { access = PAGE_CACHE_BYPASS; } switch (access & PAGE_CACHE_MASK) { case PAGE_CACHE_WB: atomctl >>= 2; - /* fall through */ + fallthrough; case PAGE_CACHE_WT: atomctl >>= 2; - /* fall through */ + fallthrough; case PAGE_CACHE_BYPASS: if ((atomctl & 0x3) == 0) { HELPER(exception_cause_vaddr)(env, pc, EXCLUSIVE_ERROR_CAUSE, vaddr); } break; case PAGE_CACHE_ISOLATE: HELPER(exception_cause_vaddr)(env, pc, LOAD_STORE_ERROR_CAUSE, vaddr); break; default: break; } } diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 54bee7ddba..8ef940933c 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -795,24 +795,24 @@ again: static void opcode_add_resource(struct slot_prop *op, uint32_t resource, char direction, int index) { switch (direction) { case 'm': case 'i': assert(op->n_in < ARRAY_SIZE(op->in)); op->in[op->n_in].resource = resource; op->in[op->n_in].index = index; ++op->n_in; - /* fall through */ + fallthrough; case 'o': if (direction == 'm' || direction == 'o') { assert(op->n_out < ARRAY_SIZE(op->out)); op->out[op->n_out].resource = resource; op->out[op->n_out].index = index; ++op->n_out; } break; default: g_assert_not_reached(); } } -- 2.39.2