: [PATCH v3 1/3] hw/block/m25p80: Fix Numonyx NVCFG DIO and QIO bit
polarity
Hi Joe,
On Thu, Nov 05, 2020 at 05:32:56PM -0800, Joe Komlodi wrote:
> QIO and DIO modes should be enabled when the bits in NVCFG are set to 0.
> This matches the behavior of the other bits in the NVCFG register
Hi Joe,
On Thu, Nov 05, 2020 at 05:32:56PM -0800, Joe Komlodi wrote:
> QIO and DIO modes should be enabled when the bits in NVCFG are set to 0.
> This matches the behavior of the other bits in the NVCFG register.
The enhanced register has the bits with the same polarities, meaning that the
value
@nongnu.org; mre...@redhat.com
Subject: Re: [PATCH v3 1/3] hw/block/m25p80: Fix Numonyx NVCFG DIO and QIO bit
polarity
On 11/6/20 2:32 AM, Joe Komlodi wrote:
> QIO and DIO modes should be enabled when the bits in NVCFG are set to 0.
> This matches the behavior of the other bits in the NVCFG registe
On 11/6/20 2:32 AM, Joe Komlodi wrote:
> QIO and DIO modes should be enabled when the bits in NVCFG are set to 0.
> This matches the behavior of the other bits in the NVCFG register.
Is this material for the 5.2 release?
>
> Signed-off-by: Joe Komlodi
> ---
> hw/block/m25p80.c | 4 ++--
> 1 fi
