For example, the memory address 0x10008000 is on an unwritable page.When the
instruction "add dword ptr [0x10007FFF],0x12345678" is executed,the OS will
set 0x10008000 page be a writable page and re-execute this instruction. But
softmmu has modifed the value of 0x10007FFF,so after re-executing thi
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer 07/10/28 01:44:40
Modified files:
target-cris: helper.c op.c
Log message:
Use the shiny new clz helpers.
CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu/target-cris/helper.c?cvsroot=q
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer 07/10/28 01:43:52
Modified files:
hw : mipsnet.c
Log message:
Less debug noise from the mipsnet driver.
CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu/hw/mipsnet.c?cvsroot=qe
> I changed Slirp output to use vectored IO to avoid the slowdown from
> memcpy (see the patch for the work in progress, gives a small
> performance improvement). But then I got the idea that using AIO would
> be nice at the outgoing end of the network IO processing. In fact,
> vectored AIO model c
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Jocelyn Mayer 07/10/28 00:56:24
Modified files:
target-alpha : cpu.h exec.h op_helper.c op_mem.h translate.c
Log message:
Alpha coding style and inlining fixes.
CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Jocelyn Mayer 07/10/28 00:55:05
Modified files:
target-ppc : helper.c op_helper.c translate.c
Log message:
PowerPC coding style and inlining fixes.
CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu/targe
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Jocelyn Mayer 07/10/27 23:34:30
Modified files:
target-ppc : op_helper.c
Log message:
PowerPC floating-point helper typo.
CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_helper.c?cvsroot=
Following the previous discussions about host-utils implementations,
here's a patch with the following changes:
- move mulu64 and muls64 definitions from exec.h to host-utils.h, for
consistency
- include host-utils.h in more files to reflect this change
- make the optimized version of mulu64 / muls
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Jocelyn Mayer 07/10/27 17:59:46
Modified files:
target-ppc : op_helper.c
Log message:
PowerPC float bugfix: 64 bits float mantissa is 52 bits long.
CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu/targe
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Jocelyn Mayer 07/10/27 17:54:30
Modified files:
darwin-user: main.c
linux-user : main.c
target-ppc : cpu.h helper.c op.c op_helper.c op_helper.h
op_template.h transla
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Jocelyn Mayer 07/10/27 17:29:35
Modified files:
linux-user : elfload.c main.c
Log message:
PowerPC user-mode fix: MSR is now entirelly set-up in the cpu_reset
routine.
CVSWeb URLs:
http://cvs.savannah.gnu.o
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Jocelyn Mayer 07/10/27 17:18:49
Modified files:
target-ppc : op_mem.h
Log message:
Fix endianness bug for PowerPC stfiwx instruction.
CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/op_mem.h
On 10/27/07, Blue Swirl <[EMAIL PROTECTED]> wrote:
> I changed Slirp output to use vectored IO to avoid the slowdown from
> memcpy (see the patch for the work in progress, gives a small
> performance improvement). But then I got the idea that using AIO would
> be nice at the outgoing end of the net
On Sat, 2007-10-27 at 15:27 +0200, Christian "Eddie" Dost wrote:
> The sparc64 popc works in O(lg(n))
No, it has a fix cost, whatever the operand is.
It has another advantage: it does not need any intermediate variable,
which is great when running on CISC host in the Qemu execution
environmnent.
The sparc64 popc works in O(lg(n)), the "optimized" code below work in
O(n). Could be better to generalize the sparc64 code, like this:
static always_inline int ctpop32 (uint32_t val)
{
uint32_t i;
i = (val & 0x) + ((val >> 1) & 0x);
i = (i & 0x333
Thayne Harbaugh wrote:
> This is a rework of Stuart Anderson's strace patch. I've fixed
> target-to-host and host-to-target syscall lookups so that the proper
> host or target errno is returned.
It didn't build for me due to the a missing target_to_host_errno
function. Could you also have a look
On Sat, 2007-10-27 at 16:01 +0300, Blue Swirl wrote:
> On 10/27/07, J. Mayer <[EMAIL PROTECTED]> wrote:
> > I also got optimized versions of bit population count which could also
> > be shared:
> > static always_inline int ctpop32 (uint32_t val)
> > {
> > int i;
> >
> > for (i = 0; val != 0
J. Mayer wrote:
>
> On Sat, 2007-10-27 at 12:19 +0100, Thiemo Seufer wrote:
> > J. Mayer wrote:
> > > The latest patches in clo makes gcc 3.4.6 fail to build the mips64
> > > targets on my amd64 host (looks like an register allocation clash in the
> > > optimizer code).
> >
> > Your version is li
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer 07/10/27 13:05:54
Modified files:
target-mips: exec.h op.c op_helper.c
Added files:
. : host-utils.h
Log message:
Add sharable clz/clo inline functions and use them for
On 10/27/07, J. Mayer <[EMAIL PROTECTED]> wrote:
> I also got optimized versions of bit population count which could also
> be shared:
> static always_inline int ctpop32 (uint32_t val)
> {
> int i;
>
> for (i = 0; val != 0; i++)
> val = val ^ (val - 1);
>
> return i;
> }
>
> If
Hi,
I changed Slirp output to use vectored IO to avoid the slowdown from
memcpy (see the patch for the work in progress, gives a small
performance improvement). But then I got the idea that using AIO would
be nice at the outgoing end of the network IO processing. In fact,
vectored AIO model could
On Sat, 2007-10-27 at 12:19 +0100, Thiemo Seufer wrote:
> J. Mayer wrote:
> > The latest patches in clo makes gcc 3.4.6 fail to build the mips64
> > targets on my amd64 host (looks like an register allocation clash in the
> > optimizer code).
>
> Your version is likely faster as well.
>
> > Furt
J. Mayer wrote:
> The latest patches in clo makes gcc 3.4.6 fail to build the mips64
> targets on my amd64 host (looks like an register allocation clash in the
> optimizer code).
Your version is likely faster as well.
> Furthermore, the clz micro-op for Mips seems very suspect to me,
> according
Blue Swirl wrote:
> On 10/24/07, Thiemo Seufer <[EMAIL PROTECTED]> wrote:
> > - SPARC and Alpha look like they will break on 32bit hosts, they should
> > do multiplications the same way as the other 64bit targets.
>
> I can't see how Sparc would break: smul and umul perform 32x32->64 bit
> multi
Rob Landley a écrit :
> On Monday 22 October 2007 11:28:10 am Aurelien Jarno wrote:
>> Signed-off-by: Aurelien Jarno <[EMAIL PROTECTED]>
>>
>> diff --git a/arch/ppc/syslib/i8259.c b/arch/ppc/syslib/i8259.c
>> index 1e5a00a..559f27c 100644
>> --- a/arch/ppc/syslib/i8259.c
>> +++ b/arch/ppc/syslib/i8
On Monday 22 October 2007 11:28:10 am Aurelien Jarno wrote:
> Signed-off-by: Aurelien Jarno <[EMAIL PROTECTED]>
>
> diff --git a/arch/ppc/syslib/i8259.c b/arch/ppc/syslib/i8259.c
> index 1e5a00a..559f27c 100644
> --- a/arch/ppc/syslib/i8259.c
> +++ b/arch/ppc/syslib/i8259.c
> @@ -127,6 +127,7 @@ st
On 10/24/07, Thiemo Seufer <[EMAIL PROTECTED]> wrote:
> - SPARC and Alpha look like they will break on 32bit hosts, they should
> do multiplications the same way as the other 64bit targets.
I can't see how Sparc would break: smul and umul perform 32x32->64 bit
multiplications, Sparc64 mulx does
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