MIPS64R2-generic implements the MIPS-3D ASE, so I assume it should
also have a 64-bit FPU. Please apply if OK.
Richard
Index: target-mips/translate_init.c
===
RCS file: /sources/qemu/qemu/target-mips/translate_init.c,v
retrieving
All MIPS COP1X instructions currently require the FPU to be in 64-bit
mode. My understanding is that this is too restrictive, and that the
base conditions are different for different revisions of the ISA:
MIPS IV:
COP1X instructions are available when the XX (CU3) bit of the
status
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer ths 07/12/28 12:35:05
Modified files:
target-mips: translate_init.c
Log message:
Set FCR0.F64 for MIPS64R2-generic, by Richard Sandiford.
CVSWeb URLs:
Pass the asi number in is_asi. This works because asi 0 is not a valid asi.
Print out the type of access (read, write, exec).
diff -p -u -r1.61 op_helper.c
--- target-sparc/op_helper.c10 Dec 2007 19:58:20 - 1.61
+++ target-sparc/op_helper.c28 Dec 2007 17:07:49 -
@@ -416,7
Add asi debug info printing.
diff -p -u -r1.61 op_helper.c
--- target-sparc/op_helper.c10 Dec 2007 19:58:20 - 1.61
+++ target-sparc/op_helper.c28 Dec 2007 17:23:29 -
@@ -6,6 +6,7 @@
//#define DEBUG_MXCC
//#define DEBUG_UNALIGNED
//#define DEBUG_UNASSIGNED
+//#define
CVSROOT:/cvsroot/qemu
Module name:qemu
Changes by: Blue Swirl blueswir1 07/12/28 18:46:01
Modified files:
hw : slavio_intctl.c
Log message:
Fix system read address mask (Robert Reif)
CVSWeb URLs:
CVSROOT:/cvsroot/qemu
Module name:qemu
Changes by: Blue Swirl blueswir1 07/12/28 18:48:39
Modified files:
hw : slavio_intctl.c
Log message:
Fix master interrupt register masking
CVSWeb URLs:
CVSROOT:/cvsroot/qemu
Module name:qemu
Changes by: Blue Swirl blueswir1 07/12/28 18:50:24
Modified files:
target-sparc : op_helper.c
Log message:
Improved ASI debugging (Robert Reif)
CVSWeb URLs:
CVSROOT:/cvsroot/qemu
Module name:qemu
Changes by: Blue Swirl blueswir1 07/12/28 20:57:43
Modified files:
. : Makefile.target qemu-doc.texi vl.c
hw : boards.h sun4m.c sun4m.h
target-sparc : op_helper.c
Added files:
hw
CVSROOT:/cvsroot/qemu
Module name:qemu
Changes by: Blue Swirl blueswir1 07/12/28 20:59:23
Modified files:
. : Makefile.target qemu-doc.texi vl.c
hw : boards.h sun4m.c sun4m.h
Added files:
hw : sun4c_intctl.c
Log
diff -p -u -r1.73 sun4m.c
--- hw/sun4m.c 28 Dec 2007 20:59:23 - 1.73
+++ hw/sun4m.c 28 Dec 2007 21:25:06 -
@@ -698,7 +698,7 @@ static const struct hwdef hwdefs[] = {
.me_irq = 30,
.cs_irq = 5,
.machine_id = 0x80,
-.iommu_version = 0x0400,
+
Richard Sandiford wrote:
All MIPS COP1X instructions currently require the FPU to be in 64-bit
mode. My understanding is that this is too restrictive, and that the
base conditions are different for different revisions of the ISA:
MIPS IV:
COP1X instructions are available when the XX
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