To enable quick runtime detection of instruction groups to the currently
selected CPU emulation, we have a feature mask of what exactly the respective
instruction supports.
This feature mask is 64 bits long and we just successfully exceeded those 64
bits. To add more features, we need to think of
Most of the code to support e500 style MMUs is already in place, but
we're missing on some of the special TLB0-TLB1 handling code and slightly
different TLB modification.
This patch adds support for the FSL style MMU.
Signed-off-by: Alexander Graf
---
target-ppc/cpu.h| 217
The MPC8544DS board emulation was only used with KVM so far, so some
parts of the code didn't provide proper values for non-KVM execution.
This patch makes the machine work without KVM enabled. To actually use
this, you also need proper e500v2 MMU emulation.
Signed-off-by: Alexander Graf
---
hw
In a global effort to get rid of KVM-only targets, this is the next
important piece of the puzzle: e500 emulation :).
We had support for running an e500 KVM guest for a while now, but the
code could not be tested without a real e500 machine, because it required
KVM to work. This patchset adds emul
The BookE specification defines MSR bit 28 as Guest State. Add it
to the list of MSR macros.
Signed-off-by: Alexander Graf
---
target-ppc/cpu.h |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 04b1259..fd599fc 100644
--- a/target
The MPC8544DS board emulation code ignored the user defined -cpu switch.
This patch enables it to only provide a sane default, not force an e500v2
CPU inside.
Signed-off-by: Alexander Graf
---
hw/ppce500_mpc8544ds.c |6 +-
1 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/hw
I forgot to mention: the patch series is at
git://repo.or.cz/qemu/rth.git rth/irq-1
Also, the i386 port defines a CPU_TARGET_MCE, checked by the kvm code,
but as far as I can tell that bit is never set. I've left that alone
for now.
r~
This interrupt name is used by i386, CRIS, and MicroBlaze.
Copy the name into each target.
Signed-off-by: Richard Henderson
---
cpu-all.h |4
poison.h|1 -
target-cris/cpu.h |3 +++
target-i386/cpu.h |1 +
target-microblaze/cpu.h |
It is no longer used anywhere.
Signed-off-by: Richard Henderson
---
cpu-all.h |1 -
poison.h |1 -
2 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/cpu-all.h b/cpu-all.h
index f813ef8..4dcd7bc 100644
--- a/cpu-all.h
+++ b/cpu-all.h
@@ -828,7 +828,6 @@ extern CPUState *cpu_
SMI, VIRQ, INIT, SIPI, and MCE are all only used by the i386 port.
Signed-off-by: Richard Henderson
---
cpu-all.h |5 -
poison.h |2 --
target-i386/cpu.h |8
3 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/cpu-all.h b/cpu-all.h
index 88c83
This bit is never set, therefore we should not read it either.
Signed-off-by: Richard Henderson
---
target-mips/exec.h |4
1 files changed, 0 insertions(+), 4 deletions(-)
diff --git a/target-mips/exec.h b/target-mips/exec.h
index b3c5a13..607edf1 100644
--- a/target-mips/exec.h
+++ b/
This interrupt name was only used by the ARM port.
Signed-off-by: Richard Henderson
---
cpu-all.h|1 -
poison.h |1 -
target-arm/cpu.h |4
3 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/cpu-all.h b/cpu-all.h
index 4dcd7bc..88c8361 100644
--- a/cpu
This mask contains all of the bits that should be ignored while single
stepping in the debugger. The mask contains 2 bits that are not currently
cleared, but are also never set. The bits are included in the mask for
consistency in handling of the CPU_INTERRUPT_TGT_EXT_N bits.
Signed-off-by: Rich
This bit is never set, therefore we should not read it either.
Signed-off-by: Richard Henderson
---
cpu-exec.c |3 ---
1 files changed, 0 insertions(+), 3 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index 5b42b25..6d43726 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -489,9 +489,6 @@ in
These defines will be place-holders for cpu-specific functionality.
Generic code will, at the end of the patch series, no longer have to
concern itself about how SMI, NMI, etc should be handled. Instead,
generic code will know only that the interrupt is internal or external.
Signed-off-by: Richar
Blue Swirl pointed out that CPU_INTERRUPT_TIMER was unused,
and should therefore be remove. This is a logical extension
of that, making all target specific cpu interrupts really be
private to the target.
This will allow new ports to define external cpu interrupts
as needed without having to modif
Signed-off-by: Stefan Weil
---
exec.c|2 +-
target-ppc/STATUS |2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/exec.c b/exec.c
index c3dc68a..ed7cffa 100644
--- a/exec.c
+++ b/exec.c
@@ -2041,7 +2041,7 @@ void cpu_physical_memory_reset_dirty(ram_addr_t sta
cppcheck reports that 'packet' is unused.
It was only used to calculate the size of the preceding data.
Removing it saves a lot of stack space (local variable rx).
Signed-off-by: Stefan Weil
---
hw/eepro100.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/eepro
port is a 32 bit register, but may be written using 8 or 16 bit writes.
Add support for byte/word writes.
Signed-off-by: Stefan Weil
---
hw/eepro100.c | 20 ++--
1 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/hw/eepro100.c b/hw/eepro100.c
index 134e146..37172a5
The general control register is a byte register.
Add support for byte reads.
Signed-off-by: Stefan Weil
---
hw/eepro100.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/hw/eepro100.c b/hw/eepro100.c
index ff8c9ba..3aee707 100644
--- a/hw/eepro100.c
+++ b/hw/eepro100.c
MDI control is a 32 bit register, but may be read or written using
8 or 16 bit access. Data is latched when the MSB is written.
Add support for byte/word read/write access.
Signed-off-by: Stefan Weil
---
hw/eepro100.c | 34 --
1 files changed, 32 insertions(+),
Like other Intel devices, e100 (eepro100) uses little endian byte order.
This patch was tested with these combinations:
i386 host, i386 + mipsel guests (le-le)
mipsel host, i386 guest (le-le)
i386 host, mips + ppc guests (le-be)
mips host, i386 guest (be-le)
mips and mipsel hosts were emulated m
When DEBUG_EEPRO100 was enabled, unsupported writes were logged twice.
Now logging in eepro100_write1 and eepro100_write2 is similar to the
logging in eepro100_write4 (which already was correct).
Signed-off-by: Stefan Weil
---
hw/eepro100.c | 14 +-
1 files changed, 9 insertions(+)
pointer is a 32 bit register, but may be written using 8 or 16 bit writes.
Add support for byte/word writes.
Signed-off-by: Stefan Weil
---
hw/eepro100.c | 33 -
1 files changed, 16 insertions(+), 17 deletions(-)
diff --git a/hw/eepro100.c b/hw/eepro100.c
index
QEMU sends frames smaller than 60 bytes to ethernet nics.
This should be fixed in the networking code because normally
such frames are rejected by real NICs and their emulations.
To avoid this behaviour, other NIC emulations pad received
frames. This patch enables this workaround for eepro100, too.
Signed-off-by: Stefan Weil
---
hw/eepro100.c |9 +
1 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/hw/eepro100.c b/hw/eepro100.c
index 3aee707..9eb43db 100644
--- a/hw/eepro100.c
+++ b/hw/eepro100.c
@@ -1442,6 +1442,10 @@ static uint32_t eepro100_read4(EEPRO100State * s
Signed-off-by: Stefan Weil
---
hw/eepro100.c | 13 ++---
1 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/hw/eepro100.c b/hw/eepro100.c
index cbbaf14..0e22d91 100644
--- a/hw/eepro100.c
+++ b/hw/eepro100.c
@@ -311,7 +311,7 @@ static const uint16_t eepro100_mdi_mask[] = {
Hi,
this is the second version of a series of patches for eepro100 which mainly
fix endianness issues and enhance register access. There was a bug report
on qemu-devel recently which is fixed by these enhancements, see
http://lists.nongnu.org/archive/html/qemu-devel/2011-03/msg02109.html.
Changes
On Sat, Apr 30, 2011 at 9:48 PM, Super Bisquit wrote:
>
> Just curious, is this for host or guest?
Guest (aka target)
> On Sat, Apr 30, 2011 at 3:32 PM, Igor Kovalenko
> wrote:
>>
>> On Sat, Apr 30, 2011 at 7:42 PM, Blue Swirl wrote:
>> > Use TCG local to work around TCG register flush due to
Just curious, is this for host or guest?
On Sat, Apr 30, 2011 at 3:32 PM, Igor Kovalenko
wrote:
> On Sat, Apr 30, 2011 at 7:42 PM, Blue Swirl wrote:
> > Use TCG local to work around TCG register flush due to a branch.
> >
> > Thanks to Artyom Tarasenko, Igor Kovalenko and Aurelien Jarno.
> >
> >
On Sat, Apr 30, 2011 at 7:42 PM, Blue Swirl wrote:
> Use TCG local to work around TCG register flush due to a branch.
>
> Thanks to Artyom Tarasenko, Igor Kovalenko and Aurelien Jarno.
>
> Signed-off-by: Blue Swirl
> ---
> I analyzed the call tree in target-sparc/translate.c for brcond* usage.
>
Use TCG local to work around TCG register flush due to a branch.
Thanks to Artyom Tarasenko, Igor Kovalenko and Aurelien Jarno.
Signed-off-by: Blue Swirl
---
I analyzed the call tree in target-sparc/translate.c for brcond* usage.
In the following lines, first level function uses brcond* directly
Anthony Liguori writes:
> On 04/20/2011 03:33 AM, Jason Wang wrote:
> > This patch adds the multiqueues support for emulated nics. Each
> > VLANClientState
> > pairs are now abstract as a queue instead of a nic, and multiple
> > VLANClientState
> > pointers were stored in the NICState and t
Anthony Liguori writes:
> On 04/20/2011 10:33 PM, Jason Wang wrote:
> > Krishna Kumar2 writes:
> > > Thanks Jason!
> > >
> > > So I can use my virtio-net guest driver and test with this patch?
> > > Please provide the script you use to start MQ guest.
> > >
> >
> > Yes and tha
>>> What is the reason for that? DisasContext itself has a pointer to env.
>>> Can it be used instead?
>>
>> DisasContext shouldn't have that pointer. Some of the decisions during
>> translation are made based on CPU model/features which don't change
>> during execution. Other decisions should be m
>>> - if possible, simcall should become a linux-user target instead
>>
>> simcall is used in freestanding libc provided by Tensilica, I guess
>> primarily to ease OS-less development. I can make it an additional
>> option, but it seems impractical to remove it completely.
>
> Does that still emula
On 30 April 2011 10:06, Blue Swirl wrote:
> On Sat, Apr 30, 2011 at 11:24 AM, Max Filippov wrote:
>> Is it worth keeping patches as small as they are now (as they only
>> reflect development chronology), or maybe it's better to consolidate
>> them on some other basis?
>
> Small patches are nicer
On Sat, Apr 30, 2011 at 11:24 AM, Max Filippov wrote:
>>> Essential ISA parts (like core opcodes, special registers, windowed
>>> registers, exceptions and interrupts) are implemented, other (like
>>> TLB, MMU, caches, coprocessors, rare opcodes) are not, although I'm
>>> planning to implement the
>> Essential ISA parts (like core opcodes, special registers, windowed
>> registers, exceptions and interrupts) are implemented, other (like
>> TLB, MMU, caches, coprocessors, rare opcodes) are not, although I'm
>> planning to implement them if/when needed.
>
> Nice work. What is the status, can th
On Fri, Apr 29, 2011 at 06:26:49PM +0530, Amit Shah wrote:
> On (Fri) 29 Apr 2011 [14:25:06], Alon Levy wrote:
> > Instead of calling flush_queued_data when unthrottling, schedule
> > a bh. That way we can return immediately to the caller, and the
> > flush uses the same call path as a have_data fo
On Sat, Apr 30, 2011 at 12:08 AM, Max Filippov wrote:
> Hello.
>
> I'm developing support for new qemu target architecture: xtensa [1],
> primarily because AFAIK there's no free/open simulator for this
> architecture.
>
> Essential ISA parts (like core opcodes, special registers, windowed
> regist
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