Re: [Qemu-devel] [PATCH 5/8] tcg: Add interpreter for bytecode

2011-09-17 Thread Stefan Weil
Am 18.09.2011 06:03, schrieb Andi Kleen: Stefan Weil writes: + + switch (opc) { + case INDEX_op_end: + case INDEX_op_nop: + break; You could probably get some more speed out of this by using a threaded interpreter with gcc's computed goto extension. That's typically significantly faster than

Re: [Qemu-devel] [PATCH 5/8] tcg: Add interpreter for bytecode

2011-09-17 Thread Andi Kleen
Stefan Weil writes: > + > +switch (opc) { > +case INDEX_op_end: > +case INDEX_op_nop: > +break; You could probably get some more speed out of this by using a threaded interpreter with gcc's computed goto extension. That's typically significantly faster than a p

[Qemu-devel] [PATCH] Fix compile when MIPS_DEBUG_DISAS is defined.

2011-09-17 Thread Eric Johnson
When MIPS_DEBUG_DISAS is defined the gen_logic_imm, gen_slt_imm, gen_cond_move, gen_logic and gen_slt functions cause errors because ctx is not defined. Fixed the functions by passing in the DisasContext. Signed-off-by: Eric Johnson --- target-mips/translate.c | 72 +--

[Qemu-devel] [PATCH] Allow microMIPS SWP and SDP to have RD equal to BASE.

2011-09-17 Thread Eric Johnson
The microMIPS SWP and SDP instructions do not modify GPRs. So their behavior is well defined when RD equals BASE. The MIPS Architecture Verification Programs (AVPs) check that they work as expected. This is required for AVPs to pass. Signed-off-by: Eric Johnson --- target-mips/translate.c |

Re: [Qemu-devel] [PATCH] Add privilege level check to several Cop0 instructions.

2011-09-17 Thread Johnson, Eric
The patch applies to a8467c7a0e8b024a18608ff7db31ca2f2297e641. -Original Message- From: qemu-devel-bounces+ericj=mips@nongnu.org [mailto:qemu-devel-bounces+ericj=mips@nongnu.org] On Behalf Of Eric Johnson Sent: Saturday, September 17, 2011 5:06 PM To: qemu-devel@nongnu.org; aurel.

[Qemu-devel] [PATCH] Add privilege level check to several Cop0 instructions.

2011-09-17 Thread Eric Johnson
The MIPS Architecture Verification Programs (AVPs) check privileged instructions for the required privilege level. These changes are needed to pass the AVP suite. Signed-off-by: Eric Johnson --- target-mips/translate.c | 10 ++ 1 files changed, 10 insertions(+), 0 deletions(-) diff -

Re: [Qemu-devel] [PATCH 3/8] tcg: Add forward declarations for local functions

2011-09-17 Thread Peter Maydell
On 17 September 2011 21:00, Stefan Weil wrote: > +/* Forward declarations for functions declared and used in tcg-target.c. */ > +static int target_parse_constraint(TCGArgConstraint *ct, const char > **pct_str); > +static void tcg_out_ld(TCGContext *s, TCGType type, int ret, int arg1, > +        

Re: [Qemu-devel] [PATCH v3 5/6] vga: Use linear mapping + dirty logging in chain 4 memory access mode

2011-09-17 Thread Blue Swirl
On Thu, Sep 15, 2011 at 11:31 AM, Avi Kivity wrote: > On 09/15/2011 01:01 PM, Benjamin Herrenschmidt wrote: >> >> >  Sure :). So the problem is that when emulating the G3 Beige machine in >> >  QEMU (default ppc32 target) we also add a PCI VGA adapter. Apparently, >> >  on x86 that PCI VGA adapter

Re: [Qemu-devel] [PATCH 8/8] ppc: Support tcg interpreter on ppc hosts

2011-09-17 Thread Stefan Weil
Am 17.09.2011 23:31, schrieb Peter Maydell: On 17 September 2011 21:00, Stefan Weil wrote: Tests of the tcg interpreter on an (emulated) ppc host needed this small change. Signed-off-by: Stefan Weil --- cache-utils.h |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/

Re: [Qemu-devel] [PATCH 8/8] ppc: Support tcg interpreter on ppc hosts

2011-09-17 Thread Peter Maydell
On 17 September 2011 21:00, Stefan Weil wrote: > Tests of the tcg interpreter on an (emulated) ppc host > needed this small change. > > Signed-off-by: Stefan Weil > --- >  cache-utils.h |    2 +- >  1 files changed, 1 insertions(+), 1 deletions(-) > > diff --git a/cache-utils.h b/cache-utils.h >

[Qemu-devel] [PATCH 3/8] tcg: Add forward declarations for local functions

2011-09-17 Thread Stefan Weil
These functions are defined in the tcg target specific file tcg-target.c. The forward declarations assert that every tcg target uses the same function prototype. Signed-off-by: Stefan Weil --- tcg/tcg.c | 16 1 files changed, 16 insertions(+), 0 deletions(-) diff --git a/tcg

[Qemu-devel] [PATCH 2/8] tcg: Don't declare TCG_TARGET_REG_BITS in tcg-target.h

2011-09-17 Thread Stefan Weil
It is now declared for all tcg targets in tcg.h, so the tcg target specific declarations are redundant. Signed-off-by: Stefan Weil --- tcg/arm/tcg-target.h |1 - tcg/hppa/tcg-target.h |4 +--- tcg/ia64/tcg-target.h |2 -- tcg/mips/tcg-target.h |1 - tcg/ppc/tcg-target.h |

[Qemu-devel] [PATCH 5/8] tcg: Add interpreter for bytecode

2011-09-17 Thread Stefan Weil
Signed-off-by: Stefan Weil --- tcg/tcg.h |4 +- tcg/tci.c | 1200 + 2 files changed, 1203 insertions(+), 1 deletions(-) create mode 100644 tcg/tci.c diff --git a/tcg/tcg.h b/tcg/tcg.h index 1859fae..c99c7ea 100644 --- a/tcg/tcg.h +

[Qemu-devel] [PATCH 6/8] tcg: Add bytecode generator for tcg interpreter

2011-09-17 Thread Stefan Weil
Unlike other tcg target code generators, this one does not generate machine code for some cpu. It generates machine independent bytecode which is interpreted later. This allows running QEMU on any host. Interpreted bytecode is slower than direct execution of generated machine code. Signed-off-by

[Qemu-devel] [PATCH 1/8] tcg: Declare TCG_TARGET_REG_BITS in tcg.h

2011-09-17 Thread Stefan Weil
TCG_TARGET_REG_BITS can be determined by the compiler, so there is no need to declare it for each individual tcg target. This is especially important for new tcg targets which will be supported by the tcg interpreter. Signed-off-by: Stefan Weil --- tcg/tcg.h | 10 ++ 1 files changed,

[Qemu-devel] [PATCH 7/8] tcg: Add tcg interpreter to configure / make

2011-09-17 Thread Stefan Weil
Signed-off-by: Stefan Weil --- Makefile.target |1 + configure | 30 -- 2 files changed, 29 insertions(+), 2 deletions(-) diff --git a/Makefile.target b/Makefile.target index 88d2f1f..a2c3a4a 100644 --- a/Makefile.target +++ b/Makefile.target @@ -69,6 +69,

[Qemu-devel] [PATCH 4/8] tcg: Add some assertions

2011-09-17 Thread Stefan Weil
Signed-off-by: Stefan Weil --- tcg/tcg.c |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index bdd7a67..30f3aef 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -794,7 +794,9 @@ static char *tcg_get_arg_str_idx(TCGContext *s, char *buf, int buf_size, {

[Qemu-devel] [PATCH 8/8] ppc: Support tcg interpreter on ppc hosts

2011-09-17 Thread Stefan Weil
Tests of the tcg interpreter on an (emulated) ppc host needed this small change. Signed-off-by: Stefan Weil --- cache-utils.h |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/cache-utils.h b/cache-utils.h index 0b65907..7c3b282 100644 --- a/cache-utils.h +++ b/cache-util

[Qemu-devel] [PATCH 0/8] tcg/interpreter: Add TCG + interpreter for bytecode (virtual machine)

2011-09-17 Thread Stefan Weil
Hello, these patches add a new code generator (TCG target) to qemu. Unlike other tcg target code generators, this one does not generate machine code for some cpu. It generates machine independent bytecode which is interpreted later. That's why I called it TCI (tiny code interpreter). I wrote mo

[Qemu-devel] [PATCH] sun4u: don't set up isa_mem_base

2011-09-17 Thread Blue Swirl
Since we use memory API in sun4u.c, after 71579cae30b53c910cd6c47ab4e683f647d36519, setting up isa_mem_base puts vga.chain4 outside of the physical address space. Fix by removing obsolete isa_mem_base set up. Signed-off-by: Blue Swirl --- hw/sun4u.c |1 - 1 files changed, 0 insertions(+), 1

[Qemu-devel] [PATCH v2] memory: simple memory tree printer

2011-09-17 Thread Blue Swirl
Add a monitor command 'info mtree' to show the memory hierarchy much like /proc/iomem in Linux. Signed-off-by: Blue Swirl --- v1->v2: use /proc/iomem format. --- memory.c | 27 +++ memory.h |2 ++ monitor.c |7 +++ 3 files changed, 36 insertions(+), 0 dele

Re: [Qemu-devel] blobstore disk format (was Re: Design of the blobstore)

2011-09-17 Thread Michael S. Tsirkin
On Fri, Sep 16, 2011 at 12:46:40PM -0400, Stefan Berger wrote: > On 09/16/2011 10:44 AM, Michael S. Tsirkin wrote: > >On Thu, Sep 15, 2011 at 10:33:13AM -0400, Stefan Berger wrote: > >>On 09/15/2011 08:28 AM, Michael S. Tsirkin wrote: > >>>So the below is a proposal for a directory scheme > >>>for

Re: [Qemu-devel] [net-next RFC V2 PATCH 0/5] Multiqueue support in tun/tap

2011-09-17 Thread Michael S. Tsirkin
On Sat, Sep 17, 2011 at 02:02:04PM +0800, Jason Wang wrote: > A wiki-page was created to narrate the detail design of all parts > involved in the multi queue implementation: > http://www.linux-kvm.org/page/Multiqueue and some basic tests result > could be seen in this page > http://www.linux-kvm.or

Re: [Qemu-devel] [PATCH] Add iSCSI support for QEMU

2011-09-17 Thread Laurent Vivier
Le jeudi 15 septembre 2011 à 08:06 +0200, Paolo Bonzini a écrit : > On 09/14/2011 06:36 PM, Orit Wasserman wrote: > > > I think NBD would be fine, especially with a flush command. > > I think NBD would be fine, especially with a flush command. > > If I remember correctly , there is a problem with

[Qemu-devel] [PATCH 1/2] hw/omap_gpmc: Add comment about FIFOTHRESHOLDSTATUS bit

2011-09-17 Thread Peter Maydell
Promote the remark about why we handle FIFOTHRESHOLDSTATUS the way we do from the commit message of de8af7fe0 to a comment in the code. Signed-off-by: Peter Maydell --- hw/omap_gpmc.c |7 +++ 1 files changed, 7 insertions(+), 0 deletions(-) diff --git a/hw/omap_gpmc.c b/hw/omap_gpmc.c i

[Qemu-devel] [PATCH 2/2] hw/omap_gpmc: Modify correct field when writing IRQSTATUS register

2011-09-17 Thread Peter Maydell
Writing to IRQSTATUS should affect irqst, not irqen -- error spotted by Andrzej Zaborowski. Signed-off-by: Peter Maydell --- hw/omap_gpmc.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/hw/omap_gpmc.c b/hw/omap_gpmc.c index e27b93c..7fc82a2 100644 --- a/hw/omap_gpmc.c

Re: [Qemu-devel] [PATCH 0/5] Only one call output register needed for 64 bit hosts

2011-09-17 Thread Blue Swirl
Thanks, applied all. On Sat, Sep 17, 2011 at 2:01 PM, Stefan Weil wrote: > Am 05.09.2011 11:06, schrieb Stefan Weil: >> >> The number of registers needed for the return value of TCG opcode >> INDEX_op_call is calculated in function tcg_gen_callN (nb_rets). >> >> It can be 0 or 1, for 32 bit hosts

Re: [Qemu-devel] [PATCH] target-i386: Fix several SSE3 instructions.

2011-09-17 Thread Blue Swirl
Thanks, applied. On Fri, Sep 16, 2011 at 3:29 PM, Max Reitz wrote: > haddp[sd], hsubp[sd] and addsubp[sd] operate on floats, thus it is > necessary to use the appropriate floating point calculation functions. > If this is not done, those functions operate merely on integers, which > is not correc

Re: [Qemu-devel] [PATCH 0/4] Remove trailing double quote limitation and add virtio_set_status trace event

2011-09-17 Thread Blue Swirl
Thanks, applied all. On Tue, Sep 13, 2011 at 12:34 PM, Stefan Hajnoczi wrote: > This series removes the tracetool parser limitation that format strings must > begin and end with double quotes.  In practice this means we need to work > around PRI*64 usage by adding dummy "" at the end of the line.

Re: [Qemu-devel] [PATCH] Makefile: Fix broken build

2011-09-17 Thread Blue Swirl
Thanks, applied. On Fri, Sep 16, 2011 at 7:50 PM, Stefan Weil wrote: > make -C mybuilddir no longer works (regression caused by commit) > 388d475815c23901010a25c845eb078d47ee0740. > > PWD is the directory of the caller (not mybuilddir), > so BUILD_DIR is set to the wrong value. > > GNU make sets

Re: [Qemu-devel] [PATCH 00/14] qdev: assign unique names to all devices (part 1)

2011-09-17 Thread Blue Swirl
On Fri, Sep 16, 2011 at 4:00 PM, Anthony Liguori wrote: > This series introduces an infrastructure to remove anonymous devices from > qdev. > Anonymous devices are one of the big gaps between qdev and QOM so removing is > a prerequisite to incrementally merging QOM. > > Besides the infrastructure

Re: [Qemu-devel] [PATCH 06/14] qdev: add ability to do QOM-style derived naming

2011-09-17 Thread Blue Swirl
On Fri, Sep 16, 2011 at 4:00 PM, Anthony Liguori wrote: > By using a prefix of "::" in the name, we can safely derive the composed > device > name from the parent device and busses name.  For instance, if the "::i440fx" > device created a device named "piix3", it would look like this: > >  static

Re: [Qemu-devel] [PATCH 24/58] PPC: E500: Add PV spinning code

2011-09-17 Thread Blue Swirl
On Sat, Sep 17, 2011 at 5:15 PM, Alexander Graf wrote: > > Am 17.09.2011 um 18:58 schrieb Blue Swirl : > >> On Wed, Sep 14, 2011 at 8:42 AM, Alexander Graf wrote: >>> CPUs that are not the boot CPU need to run in spinning code to check if they >>> should run off to execute and if so where to jump

Re: [Qemu-devel] [PATCH 33/58] KVM: update kernel headers

2011-09-17 Thread Alexander Graf
Am 17.09.2011 um 18:59 schrieb Blue Swirl : > On Wed, Sep 14, 2011 at 8:42 AM, Alexander Graf wrote: >> This patch updates the kvm kernel headers to the latest version. >> >> Signed-off-by: Alexander Graf >> --- >> linux-headers/asm-powerpc/kvm.h | 23 +++ >> linux-head

Re: [Qemu-devel] [PATCH v2 03/15] sheepdog: move coroutine send/recv function to generic code

2011-09-17 Thread MORITA Kazutaka
At Sat, 17 Sep 2011 16:49:22 +0200, Paolo Bonzini wrote: > > On 09/17/2011 08:29 AM, MORITA Kazutaka wrote: > >> > +#else > >> > +struct iovec *p = iov; > >> > +ret = 0; > >> > +while (iovlen> 0) { > >> > +int rc; > >> > +if (do_sendv) { > >>

Re: [Qemu-devel] [PATCH 24/58] PPC: E500: Add PV spinning code

2011-09-17 Thread Alexander Graf
Am 17.09.2011 um 18:58 schrieb Blue Swirl : > On Wed, Sep 14, 2011 at 8:42 AM, Alexander Graf wrote: >> CPUs that are not the boot CPU need to run in spinning code to check if they >> should run off to execute and if so where to jump to. This usually happens >> by leaving secondary CPUs looping

Re: [Qemu-devel] [PATCH 47/58] Implement POWER7's CFAR in TCG

2011-09-17 Thread Blue Swirl
On Wed, Sep 14, 2011 at 8:43 AM, Alexander Graf wrote: > From: David Gibson > > This patch implements support for the CFAR SPR on POWER7 (Come From > Address Register), which snapshots the PC value at the time of a branch or > an rfid.  The latest powerpc-next kernel also catches it and can show

Re: [Qemu-devel] [PATCH 33/58] KVM: update kernel headers

2011-09-17 Thread Blue Swirl
On Wed, Sep 14, 2011 at 8:42 AM, Alexander Graf wrote: > This patch updates the kvm kernel headers to the latest version. > > Signed-off-by: Alexander Graf > --- >  linux-headers/asm-powerpc/kvm.h  |   23 +++ >  linux-headers/asm-x86/kvm_para.h |   14 ++ >  linux-h

Re: [Qemu-devel] [PATCH 24/58] PPC: E500: Add PV spinning code

2011-09-17 Thread Blue Swirl
On Wed, Sep 14, 2011 at 8:42 AM, Alexander Graf wrote: > CPUs that are not the boot CPU need to run in spinning code to check if they > should run off to execute and if so where to jump to. This usually happens > by leaving secondary CPUs looping and checking if some variable in memory > changed.

Re: [Qemu-devel] [PATCH 14/58] device tree: add nop_node

2011-09-17 Thread Blue Swirl
On Wed, Sep 14, 2011 at 8:42 AM, Alexander Graf wrote: > We have a qemu internal abstraction layer on FDT. While I'm not fully > convinced > we need it at all, it's missing the nop_node functionality that we now need > on e500. So let's add it and think about the general future of that API later.

Re: [Qemu-devel] [PATCH v2 07/18] omap_gpmc: GPMC_IRQSTATUS is write-one-to-clear

2011-09-17 Thread Peter Maydell
On 17 September 2011 02:08, andrzej zaborowski wrote: >> --- a/hw/omap_gpmc.c >> +++ b/hw/omap_gpmc.c >> @@ -284,7 +284,7 @@ static void omap_gpmc_write(void *opaque, >> target_phys_addr_t addr, >>         break; >> >>     case 0x018:        /* GPMC_IRQSTATUS */ >> -        s->irqen = ~value; >>

Re: [Qemu-devel] [PATCH v2 03/15] sheepdog: move coroutine send/recv function to generic code

2011-09-17 Thread Paolo Bonzini
On 09/17/2011 08:29 AM, MORITA Kazutaka wrote: > +#else > +struct iovec *p = iov; > +ret = 0; > +while (iovlen> 0) { > +int rc; > +if (do_sendv) { > +rc = send(sockfd, p->iov_base, p->iov_len, 0); > +} else { >

Re: [Qemu-devel] [PATCH 0/5] Only one call output register needed for 64 bit hosts

2011-09-17 Thread Stefan Weil
Am 05.09.2011 11:06, schrieb Stefan Weil: The number of registers needed for the return value of TCG opcode INDEX_op_call is calculated in function tcg_gen_callN (nb_rets). It can be 0 or 1, for 32 bit hosts also 2 (return 64 bit value in two 32 bit registers). Some TCG implementations reserve

[Qemu-devel] [PATCH] Remove qemu_host_page_bits

2011-09-17 Thread Stefan Weil
It was introduced with commit 54936004fddc52c321cb3f9a9a51140e782bed5d as host_page_bits but never used. Signed-off-by: Stefan Weil --- cpu-all.h |1 - exec.c|4 2 files changed, 0 insertions(+), 5 deletions(-) diff --git a/cpu-all.h b/cpu-all.h index 3532026..e8143cd 100644 --

Re: [Qemu-devel] [PATCH] This patch adds a new block driver : iSCSI

2011-09-17 Thread Stefan Hajnoczi
On Fri, Sep 16, 2011 at 05:53:20PM +0200, Christoph Hellwig wrote: > On Wed, Sep 14, 2011 at 04:50:25PM +0100, Stefan Hajnoczi wrote: > > I think in this case it will not make the code nicer. Since the > > external iSCSI library is based on callbacks it would be necessary to > > write the coroutin