From: David Gibson
This patch implements support for the CFAR SPR on POWER7 (Come From
Address Register), which snapshots the PC value at the time of a branch or
an rfid. The latest powerpc-next kernel also catches it and can show it in
xmon or in the signal frames.
This works well enough to le
We have a qemu internal abstraction layer on FDT. While I'm not fully convinced
we need it at all, it's missing the nop_node functionality that we now need
on e500. So let's add it and think about the general future of that API later.
Signed-off-by: Alexander Graf
---
device_tree.c | 11 ++
We don't need mpc8544_copy_soc_cell anymore, since we're explicitly reading
host values and writing guest values respectively.
Signed-off-by: Alexander Graf
---
hw/ppce500_mpc8544ds.c | 24
1 files changed, 0 insertions(+), 24 deletions(-)
diff --git a/hw/ppce500_mpc8
The helper function read_IRQreg was always called with a specific argument on
the type of register to access. Inside the function we were simply doing a
switch on that constant argument again. It's a lot easier to just unfold this
into two separate functions and call each individually.
Reported-by
The MPIC emulation is now capable of handling up to 32 CPUs. Reflect that in
the code exporting the numbers out and fix an integer overflow while at it.
Signed-off-by: Alexander Graf
---
v1 -> v2:
- Max cpus is 15 due to cINT routing
- Report nb_cpus not MAX_CPUS in MPIC capabilities
---
From: Fabien Chouteau
While working on the emulation of the freescale p2010 (e500v2) I realized that
there's no implementation of booke's timers features. Currently mpc8544 uses
ppc_emb (ppc_emb_timers_init) which is close but not exactly like booke (for
example booke uses different SPR).
Signed
From: Elie Richa
In the current emulation of the load-and-reserve (lwarx) and
store-conditional (stwcx.) instructions, the internal reservation
mechanism is taken into account, however each CPU has its own
reservation information and this information is not synchronized between
CPUs to perform pr
Now that we have nice and shiny APIs to read out the host's clock and timebase
frequencies, let's use them in the bamboo code as well!
Signed-off-by: Alexander Graf
---
hw/ppc440_bamboo.c | 45 -
1 files changed, 12 insertions(+), 33 deletions(-)
di
The bit definitions for critical interrupt routing are in PowerPC order
(most significant bit is 0), while we end up shifting it with normal bit
order. Turn the numbers around so we actually end up fetching the
right ones.
Signed-off-by: Alexander Graf
---
hw/openpic.c | 10 +-
1 files
From: Scott Wood
Share the TLB array with KVM. This allows us to set the initial TLB
both on initial boot and reset, is useful for debugging, and could
eventually be used to support migration.
Signed-off-by: Scott Wood
Signed-off-by: Alexander Graf
---
hw/ppce500_mpc8544ds.c |2 +
target
The current IPI support in the MPIC code is incomplete and doesn't work. This
code adds proper support for IPIs in MPIC by using the IDE register to remember
which CPUs IPIs are still outstanding to. New triggers through the IPI trigger
register only add to the list of CPUs we want to IPI.
Signed-
The IPI dispatch registers are write only according to every MPIC
spec I have found. So instead of pretending you could read back something
from them, better not handle them at all.
Reported-by: Elie Richa
Signed-off-by: Alexander Graf
---
hw/openpic.c |7 ---
1 files changed, 0 inserti
During the memory API conversion, the indication on little endianness of
MMIO for the heathrow PIC got dropped. This patch adds it back again.
Signed-off-by: Alexander Graf
---
hw/heathrow_pic.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/hw/heathrow_pic.c b/hw/heat
When we screw up and issue an FDT command that doesn't work, we really need to
know immediately and usually can't continue to create the machine. To make sure
we don't need to add error checking in all device tree modification code users,
we can just add the fail checks to the qemu abstract functio
CPUs that are not the boot CPU need to run in spinning code to check if they
should run off to execute and if so where to jump to. This usually happens
by leaving secondary CPUs looping and checking if some variable in memory
changed.
In an environment like Qemu however we can be more clever. We c
Commit 23c5e4ca (convert to memory API) broke the VIA Cuda emulation layer
by not registering the IO structs.
This patch registers them properly and thus makes -M g3beige and -M mac99
work again.
Tested-by: Andreas Färber
Signed-off-by: Alexander Graf
---
hw/cuda.c | 28 -
From: Fabien Chouteau
Signed-off-by: Fabien Chouteau
Signed-off-by: Alexander Graf
---
gdbstub.c |2 +-
target-ppc/translate_init.c |3 +--
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/gdbstub.c b/gdbstub.c
index 12dd100..1d99e19 100644
--- a/gdbstub
The MPIC exports a register set for each CPU connected to it. They can all
be accessed through specific registers or using a shadow page that is mapped
differently depending on which CPU accesses it.
This patch implements the shadow map, making it possible for guests to access
the CPU local regist
Another round of KVM features, another round of kernel header updates :)
Signed-off-by: Alexander Graf
---
linux-headers/asm-powerpc/kvm.h | 40 +++
linux-headers/linux/kvm.h | 18 +
2 files changed, 58 insertions(+), 0 deletions(-)
From: Paolo Bonzini
I introduced this bug in commit 05751d3 (vscsi: always use get_sense,
2011-08-03) because at the time there was no way to expose a sense
condition to SLOF and Linux manages to work around the bug. However,
the bug becomes evident now that SCSI devices also report unit
attenti
From: David Gibson
Paulo Bonzini changed the original spapr code, which manually assigned irq
numbers for each virtual device, to allocate them automatically from the
device initialization. That allowed spapr virtual devices to be constructed
with -device, which is a good start. However, the way
Now that we have generic KVM functions to read out the host tb and clock
frequencies, let's use them in the e500 code!
Signed-off-by: Alexander Graf
---
hw/ppce500_mpc8544ds.c | 44 +---
1 files changed, 9 insertions(+), 35 deletions(-)
diff --git a/hw/
From: Paolo Bonzini
Right now the spapr devices cannot be instantiated with -device,
because the IRQs need to be passed to the spapr_*_create functions.
Do this instead in the bus's init wrapper.
This is particularly important with the conversion from scsi-disk
to scsi-{cd,hd} that Markus made.
From: David Gibson
The implementation of the XICS interrupt controller contains several
(difficult to trigger) bugs due to the fact that we were not 100%
consistent with which irq numbering we used. In most places, global
numbers were used as handled by the presentation layer, however a few
func
We only support -M pseries when certain prerequisites are met, such
as a PPC64 guest and libfdt. To only gather these requirements in
a single place, this patch introduces a new CONFIG_PSERIES variable
that gets set when all prerequisites are met.
Signed-off-by: Alexander Graf
---
Makefile.targe
On 10/05/2011 10:25 PM, Juan Quintela wrote:
Anthony Liguori wrote:
On 10/04/2011 09:49 AM, Juan Quintela wrote:
Anthony Liguori wrote:
On 09/23/2011 07:57 AM, Juan Quintela wrote:
[ much more stuff ]
It avoids s==NULL checks,
In favor of s->state == MIG_STATE_NONE.
and it also avoids
We have some code in generic kvm_ppc.c that is only used by 440. Move to
the 440 specific device code.
Signed-off-by: Alexander Graf
---
hw/ppc440_bamboo.c | 37 +++--
target-ppc/kvm_ppc.c | 30 --
target-ppc/kvm_ppc.h |1 -
3
From: David Gibson
PAPR systems support several hypercalls intended for use in real mode
debugging tools. These implement reads and writes to arbitrary guest
physical addresses. This is useful for real mode software because it
allows access to IO addresses and memory outside the RMA without goi
Now that we can so nicely find out the host's frequencies, we should also
make sure that we get them into all virtual CPUs' device tree nodes.
Signed-off-by: Alexander Graf
---
hw/ppce500_mpc8544ds.c | 10 +++---
1 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/hw/ppce500_mpc
The BookE timer code had some written-but-not-read variables. Get rid
of them.
Signed-off-by: Alexander Graf
---
hw/ppc_booke.c | 14 +-
1 files changed, 1 insertions(+), 13 deletions(-)
diff --git a/hw/ppc_booke.c b/hw/ppc_booke.c
index 3e2fff5..8871945 100644
--- a/hw/ppc_booke.
When creating a VM, we should go through smp_cpus and create a virtual CPU for
every CPU the user requested. This patch adds support for that and moves some
code around to make that more convenient.
Signed-off-by: Alexander Graf
---
hw/ppce500_mpc8544ds.c | 44 +
We use the IDE register with IPIs as a mask to keep track which processors
have already acknowledged the respective interrupt. So we need to initialize
it to 0 to make sure that it doesn't accidently fire an IPI on CPU0 when the
first IPI is triggered.
Reported-by: Elie Richa
Signed-off-by: Alexa
Hi Blue,
This is my current patch queue for ppc. Please pull.
Alex
The following changes since commit e4fc8781db7c49b0c5ac5d24762e17c59dfe0871:
Stefan Hajnoczi (1):
qed: fix use-after-free during l2 cache commit
are available in the git repository at:
git://repo.or.cz/qemu/agraf.g
From: Paolo Bonzini
Restructure common properties for sPAPR devices so that IRQ definitions
can be added in one place.
Signed-off-by: Paolo Bonzini
Cc: Alexander Graf
Cc: David Gibson
Signed-off-by: Alexander Graf
---
hw/spapr_llan.c |4 +---
hw/spapr_vio.h |5 +
hw/spapr_vsc
From: Scott Wood
Signed-off-by: Scott Wood
Signed-off-by: Alexander Graf
---
hmp-commands.hx |2 +-
monitor.c |5 ++-
target-ppc/cpu.h|2 +
target-ppc/helper.c | 88 +++
4 files changed, 94 insertions(+), 3 deletio
Update HIOR and generic register get/set.
Signed-off-by: Alexander Graf
---
linux-headers/asm-powerpc/kvm.h |2 ++
linux-headers/linux/kvm.h | 33 +
2 files changed, 35 insertions(+), 0 deletions(-)
diff --git a/linux-headers/asm-powerpc/kvm.h b/linux
From: David Gibson
This patch adds support for the H_REMOVE_BULK hypercall on the pseries
machine. Strictly speaking this isn't necessarym since the kernel will
only attempt to use this if hcall-bulk is advertised in the device tree,
which previously it was not.
Adding this support may give a m
From: Andreas Färber
Since commit 8733f609 (Fix linker scripts) linking on Linux/ppc64 fails:
LINK ppc64-linux-user/qemu-ppc64
/usr/lib64/gcc/powerpc64-suse-linux/4.3/../../../../powerpc64-suse-linux/bin/ld:/home/afaerber/qemu/ppc64.ld:84:
syntax error
collect2: ld gab 1 als Ende-Status zurü
The MPIC exports a page for each CPU that it controls. To support more than
one CPU, we need to also reserve the MMIO space according to the amount of
CPUs we want to support.
Signed-off-by: Alexander Graf
---
hw/openpic.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a
On 10/05/2011 09:45 PM, Anthony Liguori wrote:
int qemu_get_buffer(QEMUFile *f, uint8_t *buf, int size1)
{
int size, l;
Can we implement get_buffer in terms of peek_buffer and just increment
f->buf_index in get_buffer?
No, get_buffer works even if size1 is greater than the size of
The guest OS wants to know where the guest spins, so let's tell him while
updating the CPU nodes with the frequencies anyways.
Signed-off-by: Alexander Graf
---
v1 -> v2:
- use new spin table address
---
hw/ppce500_mpc8544ds.c |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
From: David Gibson
The interrupt controller presented in the device tree for the pseries
machine is manipulated by the guest only through hypervisor calls. It
has no real or emulated registers for the guest to access.
However, it currently has a bogus 'reg' property advertising a register
windo
Hello,
Actually the test case that I suggested is a bit imprecise because
creating a reservation on a CPU does not cause loss of reservation
on other CPUs (I mean in the specification). It is writing to the
memory location that causes loss of reservation. Therefore the correct
test case would be t
From: Paolo Bonzini
This also lets the user see the irq in "info qtree".
Signed-off-by: Paolo Bonzini
Cc: Alexander Graf
Cc: David Gibson
Signed-off-by: Alexander Graf
---
hw/spapr_vio.c |8 +++-
1 files changed, 7 insertions(+), 1 deletions(-)
diff --git a/hw/spapr_vio.c b/hw/spap
When running with PR KVM, we need to set HIOR directly. Thankfully there
is now a new interface to set registers individually so we can just use that
and poke HIOR into the guest vcpu's HIOR register.
While at it, this also sets SDR1 because -M pseries requires it to run.
With this patch, -M pser
From: Breno Leitao
Currently there is no implementation for set-time-of-day rtas function,
which causes the following warning "setting the clock failed (-1)" on
the guest.
This patch just creates this function, get the timedate diff and store in
the papr environment, so that the correct value wi
From: Stefan Hajnoczi
The RAM_ADDR_FMT macro hides the type of ram_addr_t so that format
strings can be safely used. Make sure to use RAM_ADDR_FMT so that the
build works on 32-bit hosts with Xen enabled. Whether Xen should affect
ppc TCG targets is questionable but a separate issue.
Signed-of
This patch updates the kvm kernel headers to the latest version.
Signed-off-by: Alexander Graf
---
linux-headers/asm-powerpc/kvm.h | 23 +++
linux-headers/asm-x86/kvm_para.h | 14 ++
linux-headers/linux/kvm.h| 25 +
linux-hea
On 6 October 2011 04:43, TusharK wrote:
> (1) Does your kernel boot on the real hardware?
> I do not have real hardware to test my kernel. But what I did was, I
> downloaded pre-built kernel image from
> http://code.google.com/p/smp-on-qemu/downloads/list website and
> tried to run using QEMU, it
When running PR style KVM, we need to tell the kernel that we want
to run in PAPR mode now. This means that we need to pass some more
register information down and enable papr mode. We also need to align
the HTAB to htab_size boundary.
Using this patch, -M pseries works with kvm even on non-hv kvm
We need to find out the host's clock-frequency when running on KVM, so
let's export a respective function.
Signed-off-by: Alexander Graf
---
v1 -> v2:
- enable 64bit values
---
target-ppc/kvm.c | 67 ++
target-ppc/kvm_ppc.h |1 +
2 f
The MPIC has some funny feature where it maps different registers to an MMIO
region depending which CPU accesses them.
To be able to reflect that, we need to make OpenPIC be compiled in the target
code, so it can access cpu_single_env.
Signed-off-by: Alexander Graf
---
Makefile.objs |1 -
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