The block layer assumes that it is the only user of coroutines -
The qemu_in_coroutine() is used to determine if a function is in one of the
block layers coroutines, which is flawed. I.E. If a client (e.g. a device or
a machine model) of the block layer uses couroutine itself, the block layer
will
From: David Gibson
Not that long ago, every device implementation using DMA directly
accessed guest memory using cpu_physical_memory_*(). This meant that
adding support for a guest visible IOMMU would require changing every
one of these devices to go through IOMMU translation.
Shortly before qe
From: David Gibson
This patch adds the basic infrastructure necessary to emulate an IOMMU
visible to the guest. The DMAContext structure is extended with
information and a callback describing the translation, and the various
DMA functions used by devices will now perform IOMMU translation using
From: David Gibson
The pseries platform already contains an IOMMU implementation, since it is
essential for the platform's paravirtualized VIO devices. This IOMMU
support is currently built into the implementation of the VIO "bus" and
the various VIO devices.
This patch converts this code to ma
From: David Gibson
The AHCI device can provide both PCI and SysBus AHCI device
emulations. For this reason, it wasn't previously converted to use
the pci_dma_*() helper functions. Now that we have universal DMA
helper functions, this converts AHCI to use them.
The DMAContext is obtained from p
From: David Gibson
The USB UHCI and EHCI drivers were converted some time ago to use the
pci_dma_*() helper functions. However, this conversion was not complete
because in some places both these drivers do DMA via the usb_packet_map()
function in usb-libhw.c. That function directly used
cpu_phy
From: David Gibson
This patch adds some hooks to let PCI devices and busses use the new IOMMU
infrastructure. When IOMMU support is enabled, each PCI device now
contains a DMAContext * which is used by the pci_dma_*() wrapper functions.
By default, the contexts are initialized to NULL, assuming
From: David Gibson
Currently the pseries machine emulation does not support DMA for emulated
PCI devices, because the PAPR spec always requires a (guest visible,
paravirtualized) IOMMU which was not implemented. Now that we have
infrastructure for IOMMU emulation, we can correct this and allow P
The emulated devices can run simultaneously with the guest, so
we need to be careful with ordering of load and stores done by
them to the guest system memory, which need to be observed in
the right order by the guest operating system.
This adds a barrier call to the basic DMA read/write ops which
From: David Gibson
The OHCI device emulation can provide both PCI and SysBus OHCI
implementations. Because of this, it was not previously converted to
use the PCI DMA helper functions.
This patch converts it to use the new universal DMA helper functions.
In the PCI case, it obtains its DMAConte
From: David Gibson
dma-helpers.c contains a number of helper functions for doing
scatter/gather DMA, and various block device related DMA. Currently,
these directly access guest memory using cpu_physical_memory_*(),
assuming no IOMMU translation.
This patch updates this code to use the new univ
From: David Gibson
A while back, we introduced the dma_addr_t type, which is supposed to
be used for bus visible memory addresses. At present, this is an
alias for target_phys_addr_t, but this will change when we eventually
add support for guest visible IOMMUs.
There are some instances of targe
Here's the latest drop as discussed on the list. 2 patches are gone,
the _set variant is folded in the DMA helpers and I ditched all the
broken cancellation bits.
On Wed, 2012-06-20 at 16:25 -0500, Anthony Liguori wrote:
> > +static void dma_aio_cancel(BlockDriverAIOCB *acb)
> > +{
> > +DMAAIOCB *dbs = container_of(acb, DMAAIOCB, common);
> > +
> > +trace_dma_aio_cancel(dbs);
> > +
> > +if (dbs->acb) {
> > +BlockDriverAIOCB *acb = dbs->a
On Thu, Jun 21, 2012 at 06:28:30PM +0100, Peter Maydell wrote:
> On 21 June 2012 18:24, Blue Swirl wrote:
> > On Wed, Jun 20, 2012 at 7:10 AM, Jia Liu wrote:
> >> ERROR: need consistent spacing around '*' (ctx:WxV)
> >> #99: FILE: target-openrisc/int_helper.c:53:
> >> +target_ulong HELPER(mul32)(
> >> +if ((i & 63) == 0) {
> >> +uint64_t t1 = (qemu_get_clock_ns(rt_clock) - bwidth) /
> >> 100;
> >> +if (t1 > 50) { /* 50ms, half buffered_file limit */
> > can't we use a constant ?
>
> 50 is a constant already, no? Or what do you mean.
I guess Orit mea
Hi Liu,
On Thu, Jun 21, 2012 at 11:06:58PM +0800, Liu Ping Fan wrote:
> In order to break the big lock, using per-cpu_lock in kvm_cpu_exec()
> to protect the race from other cpu's access to env->apic_state & related
> field in env.
Can this also be applied on tcg_cpu_exec(), too?
Regards,
chen
On Thu, 2012-06-21 at 07:55 -0500, Anthony Liguori wrote:
> As long as we scrub the buffers, returning an unhandled error seems okay to
> me.
>
> I've long thought we should have some sort of generic way to throw an error
> and
> effectively pause a single device. I'm not sure how it would wo
On 22/06/12 00:04, Andreas Färber wrote:
> Am 21.06.2012 15:10, schrieb Alexey Kardashevskiy:
>> On 21/06/12 22:19, Andreas Färber wrote:
>>> Am 21.06.2012 13:21, schrieb Alexey Kardashevskiy:
On 21/06/12 20:36, Andreas Färber wrote:
> Am 21.06.2012 05:22, schrieb Alexey Kardashevskiy:
>>>
On Wed, 2012-06-20 at 16:16 -0500, Anthony Liguori wrote:
> > diff --git a/qemu-common.h b/qemu-common.h
> > index 8f87e41..80026af 100644
> > --- a/qemu-common.h
> > +++ b/qemu-common.h
> > @@ -264,6 +264,7 @@ typedef struct EventNotifier EventNotifier;
> > typedef struct VirtIODevice VirtIODevi
On Wed, 2012-06-20 at 16:11 -0400, Jason Baron wrote:
> There are several instances of 'typedef struct DMAContext DMAContext'. Remove
> them
> all except for the one in qemu-common.h.
Actually, the other way around :-) I'm removing the one in qemu-common.h
in favor of the one in dma.h (at Anthony
On Wed, 2012-06-20 at 16:15 -0500, Anthony Liguori wrote:
> On 06/19/2012 01:39 AM, Benjamin Herrenschmidt wrote:
> > From: David Gibson
> >
> > This patch adds cpu_physical_memory_set() function. This is equivalent to
> > calling cpu_physical_memory_write() with a buffer filled with a character,
On Wed, 2012-06-20 at 16:14 -0500, Anthony Liguori wrote:
> diff --git a/hw/qdev-dma.h b/hw/qdev-dma.h
> > new file mode 100644
> > index 000..f0ff558
> > --- /dev/null
> > +++ b/hw/qdev-dma.h
> > @@ -0,0 +1,12 @@
> > +/*
> > + * Support for dma_addr_t typed properties
> > + *
> > + * Copyrig
Added (msi|msix)_set_message() function for whoever might
want to use them.
Currently msi_notify()/msix_notify() write to these vectors to
signal the guest about an interrupt so the correct values have to
written there by the guest or QEMU.
For example, POWER guest never initializes MSI/MSIX vect
On Wed, Jun 20, 2012 at 04:08:41PM +0300, Gleb Natapov wrote:
> On Tue, May 22, 2012 at 09:23:03PM -0400, Kevin O'Connor wrote:
> > On Sun, May 20, 2012 at 12:03:38PM +0300, Gleb Natapov wrote:
> > >
> > > Signed-off-by: Gleb Natapov
> >
> > The patch series looks okay to me. Let me know when t
On 21/06/12 21:49, Jan Kiszka wrote:
> On 2012-06-21 13:39, Alexey Kardashevskiy wrote:
>> Added (msi|msix)_set_message() functions.
>>
>> Currently msi_notify()/msix_notify() write to these vectors to
>> signal the guest about an interrupt so the correct values have to
>> written there by the gues
On 06/21/2012 07:51 PM, Eduardo Habkost wrote:
Hi,
I just noticed libvirt tries to use the -numa option in a way that qemu
never understood: if a node is configured to have a non-contiguous set
of CPUs, it tries to generate a command-line option that looks like:
"-numa node,nodeid=...,cpus=0,2,
Public bug reported:
Host is debian testing, on x64.
Guest is a windoze xp.
I'm flashing a mobile Point of Sale (POS) terminal using its proprietary
windoze program that communicates on serial ports. The POS device has a
USB port which is acting as a serial port (CDC to USB UART).
Up to and inc
KVM is an industry leading open source hypervisor that provides an ideal
platform for datacenter virtualization, virtual desktop infrastructure,
and cloud computing. Once again, it's time to bring together the
community of developers and users that define the KVM ecosystem for
our annual technical
From: Paolo Bonzini
FITRIM is a mounted filesystem feature to discard (or "trim") blocks which
are not in use by the filesystem. This is useful for solid-state drives
(SSDs) and thinly-provisioned storage. Provide access to the feature
from the host so that filesystems can be trimmed periodicall
From: Paolo Bonzini
We will use these functions and types for more than FSFREEZE, so rename them.
Signed-off-by: Paolo Bonzini
Reviewed-by: Luiz Capitulino
Reviewed-by: Michal Privoznik
Signed-off-by: Michael Roth
---
qga/commands-posix.c | 36 ++--
1 files
The following changes since commit 47ecbdf07ed2c37bdfd2d77137d01bb319ce13da:
libcacard: build fixes (2012-06-21 20:04:24 +)
are available in the git repository at:
git://github.com/mdroth/qemu.git qga-pull-6-21-12
Paolo Bonzini (2):
qemu-ga: make names more generic for mount list f
Add an explicit CPUX86State parameter instead of relying on AREG0.
Signed-off-by: Blue Swirl
---
target-i386/Makefile.objs |1 -
target-i386/helper.h| 50 +-
target-i386/int_helper.c| 36 +-
target-i386/shift_h
Move condition code helpers to cc_helper.c.
Move the shared inline functions lshift(), cpu_load_eflags() and
cpu_cc_compute_all() to cpu.h.
Signed-off-by: Blue Swirl
---
target-i386/Makefile.objs |3 +-
target-i386/cc_helper.c | 387 +++
target-i38
Fix coding style in helper_template.h before next commit.
Signed-off-by: Blue Swirl
---
target-i386/helper_template.h | 25 ++---
1 files changed, 22 insertions(+), 3 deletions(-)
diff --git a/target-i386/helper_template.h b/target-i386/helper_template.h
index afc41fb..8b2
After the previous patch, we can use the proper
declaration in a common header file.
Signed-off-by: Blue Swirl
---
target-i386/excp_helper.c |5 +
1 files changed, 1 insertions(+), 4 deletions(-)
diff --git a/target-i386/excp_helper.c b/target-i386/excp_helper.c
index 72bd46d..aaa5ca2 1
Adjust function names and add an explicit CPUX86State
parameter instead of relying on AREG0.
Signed-off-by: Blue Swirl
---
target-i386/op_helper.c | 68 +-
1 files changed, 37 insertions(+), 31 deletions(-)
diff --git a/target-i386/op_helper.c b/tar
Move memory access helpers to mem_helper.c.
Signed-off-by: Blue Swirl
---
target-i386/Makefile.objs |3 +-
target-i386/mem_helper.c | 161 +
target-i386/op_helper.c | 138 +--
3 files changed, 165 insertions
Move shift templates from helper_template.h to
shift_helper_template.h and the condition code helpers
to cc_helper_template.h.
Signed-off-by: Blue Swirl
---
target-i386/cc_helper_template.h| 277 +++
target-i386/helper_template.h | 353
Add an explicit CPUX86State parameter instead of relying on AREG0.
Remove temporary wrappers and switch to AREG0 free mode.
Signed-off-by: Blue Swirl
---
configure |2 +-
cpu-all.h | 22 ++
target-i386/Makefile.objs |2 -
target-i386/cpu.h |
Adding basic options to the configure script to use libseccomp or not.
The default is set to 'no'. If the flag --enable-libseccomp is used, the
script will check for its existence using pkg-config.
v2:
* As I removed all the code related to seccomp from vl.c, I created
qemu-seccomp.[ch].
* Al
I added a syscall struct using priority levels as described in the
libseccomp man page. The priority numbers are based to the frequency
they appear in a sample strace from a regular qemu guest run under
libvirt.
Libseccomp generates linear BPF code to filter system calls, those rules
are read one
Hello all,
This is the third effort to sandbox Qemu guests using Libseccomp[0]. The
patches that follows are pretty simple and straightforward. I added the correct
options and checks to the configure script and the basic calls to libseccomp in
the main loop at vl.c. Details of each one are in the
SSE function tables could easily be corrupted because of use
of void pointers.
Introduce function pointer types and helper variables in order
to improve type safety.
Split sse_op_table3 according to types used.
Signed-off-by: Blue Swirl
---
target-i386/translate.c | 134 ++
Add an explicit CPUX86State parameter instead of relying on AREG0.
Rename remains of op_helper.c to seg_helper.c.
Signed-off-by: Blue Swirl
---
target-i386/Makefile.objs |1 -
target-i386/helper.h | 38
target-i386/seg_helper.c | 217 +--
Switch to wrapped versions of memory access functions.
Signed-off-by: Blue Swirl
---
target-i386/cpu.h| 10 ++
target-i386/mem_helper.c | 10 ++
target-i386/seg_helper.c | 209 +++---
3 files changed, 126 insertions(+), 103 deletions(-)
diff
Add an explicit CPUX86State parameter instead of relying on AREG0.
Signed-off-by: Blue Swirl
---
target-i386/Makefile.objs |1 -
target-i386/helper.h | 40
target-i386/misc_helper.c | 73 ++---
target-i386/translate.c
Move integer and bit field helpers to int_helper.c.
Signed-off-by: Blue Swirl
---
target-i386/Makefile.objs |3 +-
target-i386/int_helper.c | 500 +
target-i386/op_helper.c | 478 ---
3 files changed, 50
Move various functions to misc_helper.c.
Signed-off-by: Blue Swirl
---
target-i386/Makefile.objs |3 +-
target-i386/misc_helper.c | 603 +
target-i386/op_helper.c | 578 ---
3 files changed, 605 insertion
Add an explicit CPUX86State parameter instead of relying on AREG0.
Signed-off-by: Blue Swirl
---
target-i386/Makefile.objs |1 -
target-i386/helper.h | 22 +++---
target-i386/svm_helper.c | 181 ++---
target-i386/translate.c | 21 +++---
4
Add an explicit CPUX86State parameter instead of relying on AREG0.
Signed-off-by: Blue Swirl
---
target-i386/Makefile.objs |1 -
target-i386/helper.h |2 +-
target-i386/smm_helper.c | 14 --
target-i386/translate.c |2 +-
4 files changed, 6 insertions(+), 13 del
Add an explicit CPUX86State parameter instead of relying on AREG0.
Signed-off-by: Blue Swirl
---
target-i386/Makefile.objs |1 -
target-i386/cc_helper.c | 199 +--
target-i386/cc_helper_template.h| 36 +++---
target-i386/helper.h
These still fail the test but I'll send them for review and to
complement the first series.
Blue Swirl (9):
x86: avoid AREG0 for FPU helpers
x86: avoid AREG0 for condition code helpers
x86: avoid AREG0 for integer helpers
x86: avoid AREG0 for SVM helpers
x86: avoid AREG0 for SMM helpers
Move SMM helpers to smm_helper.c.
Signed-off-by: Blue Swirl
---
target-i386/Makefile.objs |2 +
target-i386/op_helper.c | 285 -
target-i386/smm_helper.c | 307 +
3 files changed, 309 insertions(+), 285
Move exception handlers from op_helper.c to excp_helper.c.
Signed-off-by: Blue Swirl
---
target-i386/Makefile.objs |1 +
target-i386/cpu.h | 10 +++-
target-i386/excp_helper.c | 132 +
target-i386/op_helper.c | 113 ---
This series actually does not do much conversion.
These should be safe, so I'd like to apply them soon.
Further AREG0 conversions need more work.
Blue Swirl (17):
x86: prepare op_helper.c for splitting
x86: avoid AREG0 for exceptions
x86: split off exception handlers
x86: avoid an extern
Commit dcff25f2cd8c11a9368cc2369aeb0319c32d9e26 removed too many *.d
files. The directories fpu/ and tcg/ still don't use the recursive
subdir rules.
Signed-off-by: Stefan Weil
---
Makefile.target |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Makefile.target b/Makefile.t
On Thu, Jun 21, 2012 at 8:37 PM, Stefan Weil wrote:
> Replace Qemu-devel by QEMU-devel, Qemu-trivial by QEMU-trivial,
> and so on.
I suggest to remove Qemu-devel, email clients can handle filtering.
--
Sebastien Douche
Twitter: @sdouche / G+: +sdouche
Orit Wasserman wrote:
> On 05/22/2012 09:32 PM, Juan Quintela wrote:
>> cheking each 64 pages is a random magic number as good as any other.
> s/cheking/checking
Done.
>> +*/
>> +if ((i & 63) == 0) {
>> +uint64_t t1 = (qemu_get_clock_ns(rt_clock) - bwidth) / 100;
On 21 June 2012 19:37, Stefan Weil wrote:
> I suggest a small change of the QEMU related mailing lists
> (see https://lists.nongnu.org/mailman/listinfo/):
>
> Replace Qemu-devel by QEMU-devel, Qemu-trivial by QEMU-trivial,
> and so on.
>
> This matches the official project name which is QEMU (not
On 21.06.2012, at 20:09, Blue Swirl wrote:
> On Wed, Jun 20, 2012 at 8:11 PM, Alexander Graf wrote:
>> Some machines have MSR bits they reset with as enabled. Don't hardcode the
>> logic, but let the individual core implementations save their own reset
>> mask into an env variable.
>>
>> Sign
Hi,
I suggest a small change of the QEMU related mailing lists
(see https://lists.nongnu.org/mailman/listinfo/):
Replace Qemu-devel by QEMU-devel, Qemu-trivial by QEMU-trivial,
and so on.
This matches the official project name which is QEMU (not Qemu).
As far as I know, there is no convention w
Blue Swirl writes:
> On Wed, Jun 20, 2012 at 8:21 AM, Markus Armbruster wrote:
>> Blue Swirl writes:
>>
>>> On Tue, Jun 19, 2012 at 7:45 AM, Markus Armbruster
>>> wrote:
Blue Swirl writes:
> On Mon, Jun 18, 2012 at 9:10 AM, Markus Armbruster
> wrote:
>> Commit 5bbdbb4
On 20 June 2012 21:11, Alexander Graf wrote:
> + env->reset_msr = (1ULL < MSR_SF);
I assume you mean "<<" rather than "<" here and below...
-- PMM
On Wed, Jun 20, 2012 at 8:11 PM, Alexander Graf wrote:
> Some machines have MSR bits they reset with as enabled. Don't hardcode the
> logic, but let the individual core implementations save their own reset
> mask into an env variable.
>
> Signed-off-by: Alexander Graf
> ---
> target-ppc/cpu.h
Hi,
I just noticed libvirt tries to use the -numa option in a way that qemu
never understood: if a node is configured to have a non-contiguous set
of CPUs, it tries to generate a command-line option that looks like:
"-numa node,nodeid=...,cpus=0,2,4,mem=..."
^
But
On Wed, Jun 20, 2012 at 8:21 AM, Markus Armbruster wrote:
> Blue Swirl writes:
>
>> On Tue, Jun 19, 2012 at 7:45 AM, Markus Armbruster wrote:
>>> Blue Swirl writes:
>>>
On Mon, Jun 18, 2012 at 9:10 AM, Markus Armbruster
wrote:
> Commit 5bbdbb46 moved it to block.c because "other
On Wed, Jun 20, 2012 at 1:40 AM, Guan Xuetao wrote:
> On Mon, 2012-06-18 at 19:51 +, Blue Swirl wrote:
>> On Mon, Jun 18, 2012 at 9:24 AM, Guan Xuetao wrote:
>> > Coprocessor 0 is system control coprocessor, and we need get/set its
>> > contents.
>> > Also, all cache/tlb ops shoule be implem
On Wed, Jun 20, 2012 at 7:14 AM, Jia Liu wrote:
> Hi Blue,
>
> On Tue, Jun 19, 2012 at 2:28 AM, Blue Swirl wrote:
>> On Mon, Jun 18, 2012 at 1:02 AM, Jia Liu wrote:
>>> Add OpenRISC target stubs and basic cpu support.
>>>
>>> Signed-off-by: Jia Liu
>>> ---
>>> arch_init.c
On 21 June 2012 18:24, Blue Swirl wrote:
> On Wed, Jun 20, 2012 at 7:10 AM, Jia Liu wrote:
>> ERROR: need consistent spacing around '*' (ctx:WxV)
>> #99: FILE: target-openrisc/int_helper.c:53:
>> +target_ulong HELPER(mul32)(CPUOpenRISCState *env,
>>
>> It is really weird. And, I don't know how to
On Wed, Jun 20, 2012 at 7:10 AM, Jia Liu wrote:
> Hi Blue,
>
> On Tue, Jun 19, 2012 at 3:11 AM, Blue Swirl wrote:
>> On Mon, Jun 18, 2012 at 1:02 AM, Jia Liu wrote:
>>> This is the OpenCores OpenRISC 1200 support for QEMU.
>>> Full implementation of the system-model and linux-user-model support.
On Wed, Jun 20, 2012 at 2:10 AM, Guan Xuetao wrote:
> On Mon, 2012-06-18 at 19:59 +, Blue Swirl wrote:
> [snip]
>> > +
>> > +#define PUV3_DMA_CH_NR (6)
>> > +#define PUV3_DMA_CH_MASK (0xff)
>> > +#define PUV3_DMA_CH(offset) ((offset) >> 8)
>> > +
>> > +typedef struct {
>> >
On Wed, Jun 20, 2012 at 1:56 AM, Guan Xuetao wrote:
> On Mon, 2012-06-18 at 20:02 +, Blue Swirl wrote:
> [snip]
>> > diff --git a/hw/puv3.h b/hw/puv3.h
>> > new file mode 100644
>> > index 000..bcfc978
>> > --- /dev/null
>> > +++ b/hw/puv3.h
>> > @@ -0,0 +1,49 @@
>> > +/*
>> > + * Misc PKU
On 21.06.2012, at 18:04, Scott Wood wrote:
> On 06/21/2012 08:33 AM, Alexander Graf wrote:
>> The MAS registers on BookE are all 32 bit wide, except for MAS2, which
>> can hold up to 64 bit on 64 bit capable CPUs. Reflect this in the SPR
>> setting code, so that the guest can never write invalid
I confirm it works.
just compiled from commit c52acf60b6c12ff5eb58eb6ac568c159ae0c8737.
Windows XP SP3 installation iso boot and start installation process.
I tested both i368-softmmu and x86_64-softmmu targets.
thanks
Luigi
--
You received this bug notification because you are a member of qemu
Anthony,
please pull a couple of small Xen compile fixes to compile against
xen-unstable:
git://xenbits.xen.org/people/sstabellini/qemu-dm.git compile-xs
Anthony PERARD (2):
xen: Reorganize includes of Xen headers.
xenstore: Use
configure|2 +-
hw/xen_backend.c |6
Anthony,
please pull Anthony Perard's Xen PCI Passthrough series from:
git://xenbits.xen.org/people/sstabellini/qemu-dm.git xen-pt
All the generic patches have been acked by Michael, the Xen patches have
been reviewed by Konrad and me.
Allen Kay (2):
Introduce Xen PCI Passthrough, qdevic
On 06/21/2012 08:33 AM, Alexander Graf wrote:
> The MAS registers on BookE are all 32 bit wide, except for MAS2, which
> can hold up to 64 bit on 64 bit capable CPUs. Reflect this in the SPR
> setting code, so that the guest can never write invalid values in them.
>
> Signed-off-by: Alexander Graf
On Thu, 2012-06-21 at 16:04 +0200, Andreas Färber wrote:
> Am 21.06.2012 15:10, schrieb Alexey Kardashevskiy:
> > On 21/06/12 22:19, Andreas Färber wrote:
> >> Am 21.06.2012 13:21, schrieb Alexey Kardashevskiy:
> >>> On 21/06/12 20:36, Andreas Färber wrote:
> Am 21.06.2012 05:22, schrieb Alexe
On Thu, 2012-06-21 at 12:56 +0200, Jan Kiszka wrote:
> On 2012-06-21 12:50, Alexey Kardashevskiy wrote:
> > On 21/06/12 20:38, Jan Kiszka wrote:
> >> On 2012-06-21 12:28, Alexey Kardashevskiy wrote:
> >>> On 21/06/12 17:39, Jan Kiszka wrote:
> On 2012-06-21 09:18, Alexey Kardashevskiy wrote:
>
On 2012-06-21 16:49, Liu Ping Fan wrote:
> Nowadays, we use qemu_mutex_lock_iothread()/qemu_mutex_unlock_iothread() to
> protect the race to access the emulated dev launched by vcpu threads &
> iothread.
>
> But this lock is too big. We can break it down.
> These patches separate the CPUArchState
On Fri, Jun 15, 2012 at 11:49:36PM -, Michael Sabino wrote:
> Qemu 1.0.1 - Doesn't have a problem
> Qemu 1.1.0 - has the problem
> Qemu master commit eb2aeacf983a2a88a2b31e8fee067c38bd10abd3 - has the problem
I was also able to reproduce with commit:
eb2aeacf983a2a88a2b31e8fee067c38bd10abd3
In order to break the big lock, using per-cpu_lock in kvm_cpu_exec()
to protect the race from other cpu's access to env->apic_state & related
field in env.
Also, we need to protect agaist run_on_cpu().
Race condition can be like this:
1. vcpu-1 IPI vcpu-2
vcpu-3 IPI vcpu-2
Open window exi
introduce a lock for per-cpu to protect agaist accesing from
other vcpu thread.
Signed-off-by: Liu Ping Fan
---
cpu-defs.h |2 ++
cpus.c | 17 +
main-loop.h |3 +++
3 files changed, 22 insertions(+), 0 deletions(-)
diff --git a/cpu-defs.h b/cpu-defs.h
index f49e9
Nowadays, we use qemu_mutex_lock_iothread()/qemu_mutex_unlock_iothread() to
protect the race to access the emulated dev launched by vcpu threads & iothread.
But this lock is too big. We can break it down.
These patches separate the CPUArchState's protection from the other devices, so
we
can have
On 2012-06-21 16:49, Liu Ping Fan wrote:
> In order to break the big lock, using per-cpu_lock in kvm_cpu_exec()
> to protect the race from other cpu's access to env->apic_state & related
> field in env.
> Also, we need to protect agaist run_on_cpu().
>
> Race condition can be like this:
> 1. vcpu
Whatever we pass in to qemu_devtree_setprop to put into the device tree
will not get modified by that function, so it can easily be declared const.
Signed-off-by: Alexander Graf
---
device_tree.c |2 +-
device_tree.h |2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/d
On the e500 series, accessing SPR_EPR magically turns into an access at
that CPU's IACK register on the MPIC. Implement that logic to get kernels
that make use of that feature work.
Signed-off-by: Alexander Graf
---
hw/ppce500_mpc8544ds.c |1 +
target-ppc/Makefile.objs |1 +
target-ppc
This patch adds e5500's CPU initialization to the TCG CPU initialization
code.
Signed-off-by: Alexander Graf
---
v1 -> v2:
- remove reset msr vector
- clean up ivpr_mask code
---
target-ppc/translate_init.c | 96 +-
1 files changed, 93 insertions(
Recent u-boot has different defines for its gzip extract buffer, but the
common ground seems to be 64MB. So let's bump it up to that, enabling me
to load my test image again ;).
Signed-off-by: Alexander Graf
---
hw/loader.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --gi
The MAS registers on BookE are all 32 bit wide, except for MAS2, which
can hold up to 64 bit on 64 bit capable CPUs. Reflect this in the SPR
setting code, so that the guest can never write invalid values in them.
Signed-off-by: Alexander Graf
---
target-ppc/translate_init.c | 19 ++
Device trees usually have a node /compatible, which indicate which machine
type we're looking at. For quick prototyping, it can be very useful to change
the contents of that node via the command line.
Thus, introduce a new option to -machine called dt_compatible, which when
set changes the /compat
This patch set adds support to emulate an e5500 based virtual machine. We don't
have a machine model for that one yet, but with this patch set applied we can
fake the compatibility property of the MPC8544DS model into P5020DS, which
gets guest kernels working for me.
The patch set is based on my r
The number of SPRs avaiable in different PowerPC chip is still increasing. Add
definitions for the MAS7_MAS3 SPR and all currently known bits in EPCR.
Signed-off-by: Alexander Graf
---
target-ppc/cpu.h | 22 ++
1 files changed, 22 insertions(+), 0 deletions(-)
diff --git a
This patch moves the debug #ifdef'ed SPR trace generation into its
own function, so we can call it from multiple places.
Signed-off-by: Alexander Graf
---
target-ppc/translate_init.c | 30 ++
1 files changed, 18 insertions(+), 12 deletions(-)
diff --git a/target-pp
On Thu, Jun 21, 2012 at 07:55:58AM -0500, Anthony Liguori wrote:
> On 06/21/2012 02:33 AM, Michael S. Tsirkin wrote:
> >On Thu, Jun 21, 2012 at 08:02:06AM +1000, Benjamin Herrenschmidt wrote:
> >>On Wed, 2012-06-20 at 16:40 -0500, Anthony Liguori wrote:
> >>
> >>>Well let's return void in the DMA m
Am 21.06.2012 15:10, schrieb Alexey Kardashevskiy:
> On 21/06/12 22:19, Andreas Färber wrote:
>> Am 21.06.2012 13:21, schrieb Alexey Kardashevskiy:
>>> On 21/06/12 20:36, Andreas Färber wrote:
Am 21.06.2012 05:22, schrieb Alexey Kardashevskiy:
> I am trying to compile the very last qemu wi
IVPR can either hold 32 or 64 bit addresses, depending on the CPU type. Let
the CPU initialization function pass in its mask itself, so we can easily
extend it.
Signed-off-by: Alexander Graf
---
target-ppc/translate_init.c |9 +
1 files changed, 5 insertions(+), 4 deletions(-)
diff
The BookE variant of MSR_SF is MSR_CM. Implement everything it takes in TCG to
support running 64bit code with MSR_CM set.
Signed-off-by: Alexander Graf
---
target-ppc/cpu.h |9 +
target-ppc/excp_helper.c |9 +
target-ppc/mem_helper.c |2 +-
target-ppc/transl
On 64bit capable systems, MAS2 can actually hold a 64bit virtual page
address. So increase the mask for its EPN.
Signed-off-by: Alexander Graf
---
target-ppc/cpu.h |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 652a35a..ca2fc21
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