The FTPWMTMR010 is an APB device which provides up to 8 independent timers.
Signed-off-by: Kuo-Jung Su
---
hw/arm/Makefile.objs |1 +
hw/arm/faraday_a369_soc.c | 10 ++
hw/arm/ftpwmtmr010.c | 264 +
hw/arm/ftpwmtmr010.h | 31 +++
The FTTSC010 provides two operation modes to sample
the analog input voltage.
1. The manual operation mode needs to program
and control the panel drivers by software
step-by-step for the x-y position measurement.
2. The auto-scan mode provides a periodic sampling
method to conv
- Original Message -
> On 03/05/13 22:08, Eric Blake wrote:
> > On 03/04/2013 03:19 PM, Laszlo Ersek wrote:
> >> Signed-off-by: Laszlo Ersek
> >> ---
> >
> >> +# @guest-set-vcpus:
> >> +#
> >> +# Attempt to reconfigure (currently: enable/disable) logical
> >> processors inside
> >> +# t
The FTMAC110 is an Ethernet controller that provides AHB master capability
and is in full compliance with the IEEE 802.3 10/100 Mbps specifications.
Its DMA controller handles all data transfers between system memory
and on-chip memories.
It supports half-word data transfer for Linux. However it h
The FTSDC010 is a simple MMC/SD host controller and
many of its registers are similar to Arm PrimeCell PL181.
Signed-off-by: Kuo-Jung Su
---
hw/arm/Makefile.objs |1 +
hw/arm/faraday_a369_soc.c |7 +
hw/arm/ftsdc010.c | 358 +
hw/
The FTLCDC200 Color LCD controller performs translation of
pixel-coded data into the required formats and timings to
drive a variety of single/dual mono and color LCDs.
Depending on the LCD type and mode, the unpacked data can represent:
1. an actual true display gray or color value
2. an ad
The FTSSP010 is a multi-function synchronous serial port interface
controller which supports SSP, SPI, I2S, AC97 and SPDIF.
Only I2S and SPI protocol have been implemented in this patch.
Signed-off-by: Kuo-Jung Su
---
hw/arm/Makefile.objs |1 +
hw/arm/faraday.h |3 +
hw/ar
The FTNANDC021 is an integrated NAND flash controller which
re-pack the NAND flash command set with a shorter built-in opcode.
It also provides a register base interface for user to easily
access the underlying NAND flash chips, and also supports HW ECC.
However the optional hardware ECC function
Signed-off-by: Kuo-Jung Su
---
include/qemu/bitops.h | 63 -
1 file changed, 62 insertions(+), 1 deletion(-)
diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h
index affcc96..920d028 100644
--- a/include/qemu/bitops.h
+++ b/include/qemu/b
The s->addr should be reset along with the s->addrlen,
or it might have the previous address shifted to MSB
and then causes problem to nand erase operation.
Signed-off-by: Kuo-Jung Su
---
hw/nand.c |1 +
1 file changed, 1 insertion(+)
diff --git a/hw/nand.c b/hw/nand.c
index 61e918f..6b2f2b
It provides separate second, minute, hour, and day counters. The second
counter is toggled each second, the minute counter is toggled each minute,
the hour counter is toggled each hour, and the day counter is toggled each day.
The FTRTC011 provides a programmable auto-alarm function. When the seco
The FTI2C010 is a simple I2C master controller.
Signed-off-by: Kuo-Jung Su
---
hw/arm/Makefile.objs |1 +
hw/arm/faraday_a369_soc.c |6 ++
hw/arm/fti2c010.c | 216 +
hw/arm/fti2c010.h | 71 +++
4 files change
The Faraday FTDMAC020 provides eight configurable
channels for the memory-to-memory, memory-to-peripheral,
peripheral-to-peripheral, and peripheral-to-memory transfers.
Each DMA channel supports chain transfer and can be programmed
to one of the 16 handshaking channels in the hardware handshake mo
The FTWDT010 is used to prevent system from infinite loop
while software gets trapped in the deadlock.
Under the normal operation, users should restart FTWDT010
at the regular intervals before counter counts down to 0.
If the counter does reach 0, FTWDT010 will try to reset
the system by generati
The BIT6 of Status Register(SR):
SR[6] behaves the same as R/B# pin
SR[6] = 0 indicates the device is busy;
SR[6] = 1 means the device is ready
Some NAND flash controller (i.e. ftnandc021) relies on the SR[6]
to determine if the NAND flash erase/program is success or error timeout.
P.S:
It's used to perform AHB remap and QEMU RAM initialization
when the SDRAM is initialized before AHB remap process activated.
Signed-off-by: Kuo-Jung Su
---
hw/arm/Makefile.objs |1 +
hw/arm/faraday_a369_soc.c |4 +
hw/arm/ftahbc020.c| 190 +++
The FTAPBBRG020 supports the DMA functions for the AHB-to-AHB,
AHB-to-APB, APB-to-AHB, and APB-to-APB transactions.
The DMA engine can support up to 4 DMA channels (A, B, C, and D)
and 15 handshaking channels. A DMA channel granted by the arbiter
block is the only channel starts transfers. Each DM
The FTDDRII030 is a DDRII SDRAM controller which is responsible for
SDRAM initialization.
In QEMU we emulate only the SDRAM enable function.
Signed-off-by: Kuo-Jung Su
---
hw/arm/Makefile.objs |1 +
hw/arm/faraday_a369_soc.c |4 ++
hw/arm/ftddrii030.c | 170 ++
The Faraday A369 EVB is a Faraday SoC platform evalution board used for
Faraday IP functional verification based on the well-known ARM AMBA 2.0
architecture.
Signed-off-by: Kuo-Jung Su
---
hw/arm/Makefile.objs |2 +
hw/arm/faraday.h | 64
hw/arm/faraday_a369.c
The FTGMAC100 Ethernet controller has a DMA engine which handles
all data transfers between the system memory and on-chip memories.
Its DMA engine supports both 16-bits and 32-bits alignment,
and thus make it possible to support zero-copy transfer at both
Linux and WINCE.
It also has 802.1Q VLAN t
The FTINTC020 interrupt controller supports both FIQ and IRQ signals
to the microprocessor.
It can handle up to 64 configurable IRQ sources and 64 FIQ sources.
The output signals to the microprocessor can be configured as
level-high/low active or edge-rising/falling triggered.
Signed-off-by: Kuo-J
From: Dante
This patch includes the single core support to FA606TE, FA626TE,
FA616TE and FA726TE with CP15 Faraday extensions (AUX and I/D-Scratchpad).
Signed-off-by: Kuo-Jung Su
---
target-arm/cpu.c | 52 +++
target-arm/cpu.h |6 +++-
target-arm/helpe
These patches introduce Faraday A369 SoC platform support.
Here are some public documents for your reference.
http://www.faraday-tech.com/html/documentation/index.html
The partial version of faraday cpu datasheet with only
the CP15 and MPU description are available at my Google Drive:
https://d
Stefan,
I've sent V13 of patches with license changed.
Dmitry.
On Mon, Mar 4, 2013 at 4:52 PM, Dmitry Fleytman wrote:
> Oops, forgot to address this part...
>
> Is it enough to make following change:
>
> - * This work is licensed under the terms of the GNU GPL, version 2 or
> later.
> + * Thi
Signed-off-by: Dmitry Fleytman
Signed-off-by: Yan Vugenfirer
---
include/net/checksum.h | 12
net/checksum.c | 29 +
2 files changed, 41 insertions(+)
diff --git a/include/net/checksum.h b/include/net/checksum.h
index 3e7b93d..80203fb 100644
---
Signed-off-by: Dmitry Fleytman
Signed-off-by: Yan Vugenfirer
---
hw/Makefile.objs | 1 +
hw/vmxnet_rx_pkt.c | 187 ++
hw/vmxnet_rx_pkt.h | 174
hw/vmxnet_tx_pkt.c | 567 +
hw/vmxnet_tx_pkt.h | 148 ++
Signed-off-by: Dmitry Fleytman
Signed-off-by: Yan Vugenfirer
---
hw/vmware_utils.h | 143 ++
hw/vmxnet_debug.h | 115 ++
include/net/eth.h | 347 ++
net/Makefile.objs | 1 +
net/eth.c | 217
This set of patches implements VMWare VMXNET3 paravirtual NIC device.
The device supports of all the device features including offload capabilties,
VLANs and etc.
The device is tested on different OSes:
Fedora 15
Ubuntu 10.4
Centos 6.2
Windows 2008R2
Windows 2008 64bit
Windo
net_checksum_add_cont()
checksum calculation for scattered data with odd chunk sizes
net_raw_checksum()
checksum calculation for a buffer
Signed-off-by: Dmitry Fleytman
Signed-off-by: Yan Vugenfirer
---
include/net/checksum.h | 14 +-
net/checksum.c | 13 +++--
2 fi
On Wed, Mar 6, 2013 at 3:01 AM, Alexander Graf wrote:
> This patch adds all the prerequisites for AArch64 support that didn't
> fit into split up patches. It extends important bits in the core cpu
> headers to also take AArch64 mode into account.
>
> Signed-off-by: Alexander Graf
> ---
> include
(This mail was previously sent by accident to Alexander only.)
On Wed, Mar 6, 2013 at 3:01 AM, Alexander Graf wrote:
> We should translate AArch64 mode separately from AArch32 mode. In AArch64
> mode,
> registers look vastly different, instruction encoding is completely different,
> basically th
Hi,
Cool work and thanks for early sharing.
On Wed, Mar 06, 2013 at 03:01:15AM +0100, Alexander Graf wrote:
> Glibc 1.17 checks for the host kernel version on startup. Unfortunately,
> it also checks whether the host kernel version is recent enough for the
> target to run at all.
>
> Since AArch
On 6 March 2013 10:01, Alexander Graf wrote:
> If we want to compile a target machine type that is AArch64 capable,
> we need to add a new 64-bit capable ARM target. To make things easily
> understandable, I call this arm64. That way we are
>
> 1) Compatible with Linux
> 2) In line with the ot
On Wed, Mar 06, 2013 at 01:50:27PM +0800, Jason Wang wrote:
> Follow commit 921ac5d0f3a0df869db5ce4edf752f51d8b1596a (virtio-net: remove
> layout assumptions for ctrl vq), this patch makes multiqueue ctrl handling not
> reply on the layout of descriptors.
>
> Signed-off-by: Jason Wang
Applied, t
On (Fri) 01 Mar 2013 [10:51:33], Paolo Bonzini wrote:
> Il 01/03/2013 01:36, Eric Blake ha scritto:
> > For fd passing to work, we have to use qemu_open() instead of raw
> > open(). Is there any way to enforce that all files being opened by qemu
> > go through the appropriate qemu_open() wrapper?
On 03/05/13 18:00, Erik Rull wrote:
> Hi all,
>
> is it meanwhile possible to get the same screen output on a screen and
> on VNC? I would like to offer a "direct" terminal (with a real screen
> and keyboard) for user interaction and a VNC remote terminal e.g. for
> service access.
>
> Is it poss
> Hi, Paolo
> Do you think static buffer in qemu_file should be also removed?
Orit is working on that.
Paolo
On Wed, Mar 06, 2013 at 11:05:15AM +0900, Yeongkyoon Lee wrote:
> On 03/05/2013 11:18 PM, Aurélien Jarno wrote:
> >On Mon, Mar 04, 2013 at 05:37:31PM +0100, Aurélien Jarno wrote:
> >>Hi,
> >>
> >>On Sat, Feb 23, 2013 at 11:10:18PM +0100, Stefan Weil wrote:
> >>>This assertion occured with latest gi
Follow commit 921ac5d0f3a0df869db5ce4edf752f51d8b1596a (virtio-net: remove
layout assumptions for ctrl vq), this patch makes multiqueue ctrl handling not
reply on the layout of descriptors.
Signed-off-by: Jason Wang
---
hw/virtio-net.c | 23 ---
1 files changed, 12 insertio
BEHAVIOUR CHANGE
The ppc hash mmu hashes each virtual address to a primary and secondary
possible hash bucket (aka PTE group or PTEG) each with 8 PTEs. Then we
need a linear search through the PTEs to find the correct one for the
virtual address we're translating.
It is a programming error for t
Version 2.06 of the Power architecture describes an additional page
protection mechanism. Each virtual page has a "class" (0-31) recorded in
the PTE. The AMR register contains bits which can prohibit reads and/or
writes on a class by class basis. Interestingly, the AMR is userspace
readable and
More recent 64-bit hash MMUs support multiple page sizes, and PTEs for
large pages only include the offset of the whole large page. But the qemu
tlb only handles pages of the base size (4k) so we need to break up the
large pages into 4k pieces for the qemu tlb. To do that we have a somewhat
awkwa
BEHAVIOUR CHANGE
Currently if ppc_hash{32,64}_translate() finds a PTE matching the given
virtual address, it will always update the PTE's R & C (Referenced and
Changed) bits. This happens even if the PTE's permissions mean we are
about to deny the translation.
This is clearly a bug, although we
In the code for handling BATs, the hash32_bat_size_prot() and
hash32_bat_601_size_prot() functions are passed the BAT contents by
reference (pointer) for no clear reason, since they only need the values
within.
This patch removes this odd usage, and uses the resulting change to clean
up the caller
ppc_hash{32,64}_handle_mmu_fault() is now the only caller of
ppc_hash{32,64{_translate(), so this patch combines them together. This
means that instead of one returning a variety of non-obvious error codes
which then get translated into the various mmu exception conditions, we can
just generate th
find_pte{32,64{() do several things. First they search through a PTEG
ooking for a PTE matching our virtual address. Then they do permissions
checking and other processing on that PTE.
This patch separates the search by VA out from the rest. The search is
combined with the pte{32,64}_match() fu
On 6 March 2013 11:30, 陳韋任 (Wei-Ren Chen) wrote:
> While searching for QEMU SIMD issues, I found there was a paper presented
> in 2011 [1], and the source code is also public on [2]. However, it seems
> this project doesn't make any progress since last year. I update their
> change to upstream and
Currently the hash mmu versionsof get_phys_page_debug() use the same
ppc64_hash64_translate() function to do the translation logic as the normal
mm fault handler code.
That sounds like a good idea, but has some complications. The debug path
doesn't need, or even want some parts of the full transla
The eaddr field of mmu_ctx_hash{32,64} is effectively just used to pass the
effective address from get_segment{32,64}() to find_pte{32,64}(). Just
pass it as a normal parameter instead.
Signed-off-by: David Gibson
---
target-ppc/mmu-hash32.c | 12 +---
target-ppc/mmu-hash64.c | 12 +
This further separates the unusual case handling of direct store segments
from the main translation path by moving its logic into a helper function,
with some tiny cleanups along the way.
Signed-off-by: David Gibson
---
target-ppc/mmu-hash32.c | 117 -
Currently checking of PTE permission bits is split messily amongst
ppc_hash{32,64}_pp_check(), ppc_hash{32,64}_check_prot() and their callers.
This patch cleans this up to have the new function
ppc_hash{32,64}_pte_prot() compute the page permissions from the SLBE (for
64-bit) or segment register (3
At present a large chunk of ppc_hash32_translate() is taken up with an
ugly if selecting between direct store segments (hardly ever used) and
normal paged segments. This patch clarifies the flow of code by
handling direct store segments immediately then returning, leaving the
straight line code to
Currently the ppc_hash{32,64}_pte_update_flags() helper functions update a
PTE's referenced and changed bits as necessary to reflect the access. It
is somewhat long winded, though. This patch open codes them in their
(single) callers, in a simpler way.
Signed-off-by: David Gibson
---
target-pp
On 6 March 2013 10:01, Alexander Graf wrote:
> If we want to compile a target machine type that is AArch64 capable,
> we need to add a new 64-bit capable ARM target. To make things easily
> understandable, I call this arm64.
We may have to have a naming argument later but I want to think
my posit
BEHAVIOUR CHANGE
Currently, for 64-bit hash mmu, the execute protection bit placed into the
qemu tlb is based only on the N (No execute) bit from the PTE. However,
No Execute can also be set at the segment level. We do check this on
execute faults, but this still means we could incorrectly allow
The functions for looking up BATs (Block Address Translation - essentially
a level 0 TLB) are shared between the classic 32-bit hash MMUs and the
6xx style software loaded TLB implementations.
This patch splits out a copy for the 32-bit hash MMUs, to facilitate
cleaning it up. The remaining versi
BEHAVIOUR CHANGE
At present we take the whole of word 1 of the hash PTE as the real page
number used to calculate the translated address. This is incorrect,
because it leaves the flags from the low bits of PTE word 1 in place in the
rpm. We mostly get away with that because the value is later ma
This patch makes a general cleanup of the ppc_hash32_get_bat() function,
renaming it to ppc_hash32_bat_lookup(). In particular, the new function
only looks for a matching BAT, with the permissions check from the old
function moved to the caller.
Signed-off-by: David Gibson
---
target-ppc/mmu-ha
Currently cpu.h contains a number of definitions relating to the 64-bit
hash MMU. Some are used in the MMU emulation code, but some are only used
in the spapr MMU management hcall implementations.
This patch moves these definitions (except for a few that are needed
more widely) into mmu-hash64.h
Previous cleanups have meant the nx field of the mmu_ctx_hash32 structure
is now only used within ppc_hash32_translate(), and so it can be replaced
by a local variable.
Signed-off-by: David Gibson
---
target-ppc/mmu-hash32.c |8
1 file changed, 4 insertions(+), 4 deletions(-)
diff
The code to search for a matching BAT for a virtual address is somewhat
longwinded and awkward. In particular, it relies on seperate size and
validity information being returned from the hash32_bat_size() function
(and 601 specific variant).
We simplify this by having hash32_bat_size() return ins
On the ppc hash mmus, no-execute can be set at the segment level (on more
recent 64-bit hash mmus it can also be set at the page level). This patch
separates out this check to make it clearer what is going on, and avoiding
excessive indentation of the remaining translation code.
Signed-off-by: Da
hash32_bat_size_prot() and its 601 variant, as the name suggests, returns
both a BAT's size - needed to search for a matching BAT - and its
permissions, only relevant once a matching BAT has been located.
There's no particular advantage to combining these, so we split these roles
into seperate fun
BEHAVIOUR CHANGE
Currently, on any failure translating an address with BATs, we proceed to
normal segment and page table translation. That's incorrect if the
BAT error was due to permissions, rather than not finding a matching BAT.
We've gotten away with it because a guest would not usually put
t
On real hardware the ppc hash page table is stored in memory; accordingly
our mmu emulation code can read a hash page table in guest memory. But,
when paravirtualized under PAPR, the real hash page table is in host
memory, accessible to the guest only via hypercalls. We model this by
also allowin
find_pte{32,64}() are poorly named, since they both find a PTE and do
permissions checking of it. This patch makes them only locate a matching
PTE, moving the permission checking and other logic to the caller. We
rename the resulting search functions ppc_hash{32,64}_htab_lookup().
Signed-off-by:
With previous cleanups made, the 32-bit and 64-bit pte_check*() functions
are pretty trivial and only have one call site. This patch therefore
clarifies the overall code flow by folding those functions into their
call site.
Signed-off-by: David Gibson
---
target-ppc/mmu-hash32.c | 48
32-bit and 64-bit hash MMU implementations currently share a find_pte
function. This results in a whole bunch of ugly conditionals in the shared
function, and not all that much actually shared code.
This patch separates out the 32-bit and 64-bit versions, putting then
in mmu-hash64.c and mmu-has3
The newly separated paths for hash mmus rely on several helper functions
which are still shared with 32-bit hash mmus: pp_check(), check_prot() and
pte_update_flags(). While these don't have ugly ifdefs on the mmu type,
they're not very well thought out, so sharing them impedes cleaning up the
has
find_pte{32,64}() are not particularly well named. They only "find" a PTE
within a given PTE group, and they also do permissions checking and other
things.
This patch makes it somewhat close to matching the name, by folding the
search of both primary and secondary hash bucket into it, along with
This patch makes a general cleanup of the address mangling logic in
ppc_hash64_htab_lookup(). In particular it now avoids repeatedly switching
on the segment size. The lack of SLB and multiple segment sizes on 32-bit
means an analogous cleanup is not needed there.
Signed-off-by: David Gibson
--
cpu_ppc_handle_mmu_fault() calls get_physical_address() (whose behaviour
depends on MMU type) then, if that fails, issues an appropriate exception
- which again has a number of dependencies on MMU type.
This patch starts converting cpu_ppc_handle_mmu_fault() to have a
single switch on MMU type, ca
cpu_get_phys_page_debug() is a trivial wrapper around
get_physical_address(). But even the signature of
get_physical_address() has some things we'd like to clean up on a
per-mmu basis, so this patch moves the test on mmu model out to
cpu_get_phys_page_debug(), moving the version for 64-bit hash MM
After previous work, ppc_hash{32,64}_get_physical_address() are almost
trivial wrappers around get_segment{32,64}() which does nearly all the work of
translating an address according to the hash mmu model. Therefore combine the
two functions into one, under the better name of
ppc_hash{32,64}_trans
In ppc env->access_type is updated by e.g. integer load/stores with
ACCESS_INT floating point load/stores with ACCESS_FLOAT and so forth. In
hash mmu fault paths it can also b set to ACCESS_CODE for instruction
fetch accesses.
But the only place which uses anything more of the access_type than
wh
The get_pteg_offset() helper function is currently shared between 32-bit
and 64-bit hash mmus, taking a parameter for the hash pte size. In the
64-bit paths, it's only called in one place, and it's a trivial
calculation. This patch, therefore, open codes it for 64-bit. The
remaining version, whi
The poorly named get_segment() function handles most of the address
translation logic for hash-based MMUs. It has many ugly conditionals on
whether the MMU is 32-bit or 64-bit.
This patch splits the function into 32 and 64-bit versions, using the
switch on mmu_type that's already in the caller
(g
The PowerPC 620 was the very first 64-bit PowerPC implementation, but
hardly anyone ever actually used the chips. qemu notionally supports the
620, but since we don't actually have code to implement the segment table,
the support is broken (quite likely in other ways too).
This patch, therefore,
Currently support for both 32-bit and 64-bit hash MMUs share an
implementation of pte_check. But there are enough differences that this
means the shared function has several very ugly conditionals on "is_64b".
This patch cleans things up by separating out the 64-bit version
(putting it into mmu-h
Depending on the MSR state, for 64-bit hash MMUs, get_physical_address
can either call check_physical (which has further tests for mmu type)
or get_segment64. Similarly for 32-bit hash MMUs we can either call
check_physucal or get_bat() and get_segment32().
This patch splits off the whole get_phy
The nx field in mmu_ctx_hash64 is used in two different functions. But its
used for slightly different things in each place, and the value is never
propagated between them. In other words, it might as well be two local
variables. This patch makes it so.
Signed-off-by: David Gibson
---
target-
As a first step to disentangling the handling for 64-bit hash MMUs from
the rest, we move the code handling the Segment Lookaside Buffer (SLB)
(which only exists on 64-bit hash MMUs) into a new mmu-hash64.c file.
Signed-off-by: David Gibson
---
target-ppc/Makefile.objs |5 +-
target-ppc/cpu.
mmu_ctx_t is currently defined in cpu.h. However it is used for temporary
information relating to mmu translation, and is only used in mmu_helper.c
and (now) mmu-hash{32,64}.c. Furthermore it contains information which
should be specific to particular MMU types. Therefore, move its definition
to
Currently get_physical_address() first checks to see if translation is
enabled in the MSR, then in the translation on case switches on the mmu
type. Except that for BookE MMUs, translation is always on, and so it
has to switch in the "translation off" case as well and do the same thing
as the tran
This removes the never-used pte64_invalidate() function, and makes
ppcmas_tlb_check() static, since it's only used within that file.
Signed-off-by: David Gibson
---
target-ppc/cpu.h|3 ---
target-ppc/mmu_helper.c | 11 +++
2 files changed, 3 insertions(+), 11 deletions(-)
One LOG_MMU statement in mmu_helper.c has an odd check on the effective
address being translated. I can see no reason for this; I suspect it was
a debugging hack from long ago. This patch removes it.
Signed-off-by: David Gibson
---
target-ppc/mmu_helper.c | 10 --
1 file changed, 4 i
I'm still waiting on the CPU qomification to hit upstream so I can
update this series to apply on top of that, and change the top-level
dispatch from a switch on mmu_model to qom methods on the CPU. Other
than that, I think it's ready to go.
Hi all,
While searching for QEMU SIMD issues, I found there was a paper presented
in 2011 [1], and the source code is also public on [2]. However, it seems
this project doesn't make any progress since last year. I update their
change to upstream and you can download from here:
$ git clone git:/
On 03/05/2013 11:59 PM, Stefan Hajnoczi wrote:
>> I am looking for a way to help improving qemu block performance.
>> >
>> > APIC-V is a work in progress and the two options with public code are
>> > vhost-*
>> > and virtio-blk-dataplane.
>> >
>> > The way of doing seems very similar (bypassing th
Hi Paolo,
On Wed, Mar 6, 2013 at 5:00 AM, Paolo Bonzini wrote:
> On the x86, some devices need access to the CPU reset pin (INIT#).
> Provide a generic service to do this, using one of the internal
> cpu_interrupt targets. Generalize the PPC-specific code for
> CPU_INTERRUPT_RESET to other targe
There is some work ongoing at different places to add AArch64 (ARM64) support
to QEMU. Most of that work is currently happening behind closed doors that
won't open during the next few days.
But we should at least try and get the bits that are uncontroversial into QEMU,
so that everyone can base of
在 2013-03-05二的 20:00 +0100，Paolo Bonzini写道：
> Do not do a hard reset for port 92h, keyboard controller, or cf9h soft reset.
> These only reset the CPU.
>
> Reviewed-by: Anthony Liguori
> Signed-off-by: Paolo Bonzini
> ---
> hw/lpc_ich9.c | 7 ++-
> hw/pc.c | 3 ++-
> hw/pckbd.c| 5
The AArch64 syscall definitions are all publicly available in the Linux
kernel. Let's add them to our linux-user emulation target, so that we
can easily handle AArch64 syscalls.
Signed-off-by: Alexander Graf
---
linux-user/arm/syscall_nr.h | 326 +++
linu
From: Andreas Schwab
This patch adds signal handling for AArch64. The code is based on the
respective source in the Linux kernel.
Signed-off-by: Andreas Schwab
Signed-off-by: Alexander Graf
---
linux-user/arm/target_signal.h |4 +
linux-user/signal.c| 263
On 03/05/2013 11:18 PM, Aurélien Jarno wrote:
On Mon, Mar 04, 2013 at 05:37:31PM +0100, Aurélien Jarno wrote:
Hi,
On Sat, Feb 23, 2013 at 11:10:18PM +0100, Stefan Weil wrote:
This assertion occured with latest git master:
qemu-system-mipsel: /src/qemu/tcg/tcg-op.h:2589:
tcg_gen_goto_tb: Ass
32-bit ARM has a lot of different names for different types of CPUs it supports.
On AArch64, we don't have this, so we really don't want to execute the 32-bit
logic. Stub it out for AArch64 linux-user guests.
Signed-off-by: Alexander Graf
---
linux-user/cpu-uname.c |3 ++-
1 files changed, 2
We will need to share the disassembly status struct between AArch32 and
AArch64 modes. So put it into a header file that both sides can use.
Signed-off-by: Alexander Graf
---
target-arm/translate.c | 24 +---
target-arm/translate.h | 27 +++
2 file
We should translate AArch64 mode separately from AArch32 mode. In AArch64 mode,
registers look vastly different, instruction encoding is completely different,
basically the system turns into a different machine.
So let's do a simple if() in translate.c to decide whether we can handle the
current c
This patch adds support for AArch64 in all the small corners of
linux-user and beyond.
Signed-off-by: Alexander Graf
---
default-configs/arm64-linux-user.mak |3 ++
linux-user/arm/syscall.h | 46 +
linux-user/elfload.c | 15
Glibc 1.17 checks for the host kernel version on startup. Unfortunately,
it also checks whether the host kernel version is recent enough for the
target to run at all.
Since AArch64 support only got introduced in 3.8.0, that means that glibc
refuses to run on any older kernel version than that.
To
1 - 100 of 323 matches
Mail list logo
