From: Heinz Graalfs
Handle busy conditions (errno=EAGAIN) in char layer by using
the new char layer in the sclp console.
Signed-off-by: Heinz Graalfs
Signed-off-by: Christian Borntraeger
---
hw/char/sclpconsole.c | 18 +-
1 file changed, 1 insertion(+), 17 deletions(-)
diff -
From: Thomas Huth
The IO instructions MSCH, SSCH, STSCH, TSCH, STCRW and TPI require
that the second operand address must be aligned on a word boundary.
Signed-off-by: Thomas Huth
Reviewed-by: Cornelia Huck
Signed-off-by: Christian Borntraeger
---
target-s390x/ioinst.c | 25 +
From: Thomas Huth
Removed the redundant return code statement from handle_instruction() - it
always returned 0 and never reports any errors to its caller, since errors
from the sub-functions are already reported via program exceptions instead.
Signed-off-by: Thomas Huth
Signed-off-by: CHristian
From: Michael Mueller
When running with trace backend e.g. "simple" the writer thread needs to be
implemented in the same process context as the trace points that will be
processed. Under libvirtd control, qemu gets first started in daemonized
mode to privide its capabilities. Creating the writer
A previous commit, "seccomp: add the asynchronous I/O syscalls to the
whitelist", added several asynchronous I/O syscalls but left out the
io_submit() and io_cancel() syscalls. This patch corrects this by
adding the two missing asynchronous I/O syscalls.
Signed-off-by: Paul Moore
---
qemu-secco
Yes, that seems to work nicely, at least as far as CMOV itself is
concerned.
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https://bugs.launchpad.net/bugs/1201446
Title:
Instructions not supported by targeted CPU do not throw SIG
On Monday, July 15, 2013 02:29:37 PM Eduardo Otubo wrote:
> Since libseccomp 2.0 there's no need to check the architecture type
> anymore.
>
> Signed-off-by: Eduardo Otubo
> ---
> qemu-seccomp.c | 13 -
> 1 file changed, 13 deletions(-)
Good, this should make long term maintenance e
On 07/15/13 18:03, Michael S. Tsirkin wrote:
> On Mon, Jul 15, 2013 at 03:22:33PM +0200, Laszlo Ersek wrote:
>> On 07/10/13 15:51, Michael S. Tsirkin wrote:
>>
>>> @@ -697,7 +703,12 @@ static void rom_reset(void *unused)
>>> if (rom->data == NULL) {
>>> continue;
>>>
On Thu, Jul 11, 2013 at 10:28:15PM +0800, Amos Kong wrote:
> Markus added some comments on old patchset, this patch contains
> some additional fixes, it's based on MST's PCI tree.
>
> * Fix typos (missed 1.6, NIC)
> * Don't initialize list point at its declaration
> * Always notify QMP client if m
This patch adds sync modes on top of the work that Stefan Hajnoczi has done.
These patches apply on kevin/block with
'[PATCH] block: add drive_backup HMP command' also applied.
Hopefully all is in order as this is my first QEMU patch. Many thanks to
Stephan and Fam Zheng for their help.
V2:
This patch adds sync-modes to the drive-backup interface and
implements the FULL, NONE and TOP modes of synchronization.
FULL performs as before copying the entire contents of the drive
while preserving the point-in-time using CoW.
NONE only copies new writes to the target drive.
TOP copies change
This patch adds tests for sync modes top and none.
Signed-off-by: Ian Main
---
tests/qemu-iotests/055| 67 ---
tests/qemu-iotests/055.out| 4 +--
tests/qemu-iotests/group | 2 +-
tests/qemu-iotests/iotests.py | 5
4 files changed,
Sorry for the problem on my keyboard:
on the subject, please do s/gtom/from
On 07/15/2013 02:29 PM, Eduardo Otubo wrote:
Signed-off-by: Eduardo Otubo
---
qemu-seccomp.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/qemu-seccomp.c b/qemu-seccomp.c
index 1d5fd71..bfd372a 100644
---
On Mon, Jul 15, 2013 at 12:50:39PM +0200, Paolo Bonzini wrote:
> Il 08/07/2013 11:21, Fam Zheng ha scritto:
> > > Should the source be "bs" for MIRROR_SYNC_MODE_NONE? Also in this case
> > > you may want to default the format to "qcow2" instead of bs's format.
> >
> > Maybe not. "source" only aff
Patch which I think should fix this bug:
http://patchwork.ozlabs.org/patch/259148/
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https://bugs.launchpad.net/bugs/1201446
Title:
Instructions not supported by targeted CPU do not thr
Hello all,
In this small patch series I basically:
1) Remove the ifdef's for the (not so) new libseccomp version that does
a
best effort and translates x86_32 syscalls into x86_64 when possible.
2) Remove unused syscalls on the seccomp whitelist. For that removal, I've
been
runni
Hello all,
In this small patch series I basically:
1) Remove the ifdef's for the (not so) new libseccomp version that does
a
best effort and translates x86_32 syscalls into x86_64 when possible.
2) Remove unused syscalls on the seccomp whitelist. For that removal, I've
been
runni
Since libseccomp 2.0 there's no need to check the architecture type
anymore.
Signed-off-by: Eduardo Otubo
---
qemu-seccomp.c | 13 -
1 file changed, 13 deletions(-)
diff --git a/qemu-seccomp.c b/qemu-seccomp.c
index ca123bf..1d5fd71 100644
--- a/qemu-seccomp.c
+++ b/qemu-seccomp.c
@
Signed-off-by: Eduardo Otubo
---
qemu-seccomp.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/qemu-seccomp.c b/qemu-seccomp.c
index 1d5fd71..bfd372a 100644
--- a/qemu-seccomp.c
+++ b/qemu-seccomp.c
@@ -108,7 +108,6 @@ static const struct QemuSeccompSyscall seccomp_whitelist[]
= {
Adds VSS provider and requester as a qga-vss.dll, which is loaded by
Windows VSS service as well as by qemu-ga.
"provider.cpp" implements a basic stub of a software VSS provider.
Currently, this module only relays a frozen event from VSS service to the
agent, and thaw event from the agent to VSS s
Il 15/07/2013 18:52, Anthony Liguori ha scritto:
> Cornelia Huck writes:
>
>> The following changes since commit c3cb8e77804313e1be99b5f28a34a346736707a5:
>>
>> ioport: remove LITTLE_ENDIAN mark for portio (2013-07-12 14:37:47 -0500)
>>
>> are available in the git repository at:
>>
>> git://g
The instructions CMOVcc, FCMOVcc and F[U]COMI[P] should only be
present if the CMOV feature bit is set. Add missing feature bit
checks so we correctly fault if emulating a 486 or 586.
This fixes bug LP:1201446.
Signed-off-by: Peter Maydell
---
target-i386/translate.c | 19 +++
On Mon, Jul 15, 2013 at 07:10:30PM +0200, Paolo Bonzini wrote:
> Il 15/07/2013 19:05, Vasilis Liaskovitis ha scritto:
> > from what i understand, we are currently favoring this numa option? (I saw
> > it
> > mentioned in Gao's numa patchset series as well)
>
> The two patchsets have some overlap,
Il 15/07/2013 19:05, Vasilis Liaskovitis ha scritto:
> from what i understand, we are currently favoring this numa option? (I saw it
> mentioned in Gao's numa patchset series as well)
The two patchsets have some overlap, so it's good to find a design that
fits both.
> There is still the question
Hi,
On Thu, Jun 27, 2013 at 08:55:25AM +0200, Paolo Bonzini wrote:
> Il 27/06/2013 07:08, Wanlong Gao ha scritto:
> > Do we really need to specify the memory range? I suspect that we can
> > follow current design of normal memory in hot-plug memory.
>
> I think we can do both. I'm afraid that th
Il 15/07/2013 16:42, Stefan Hajnoczi ha scritto:
> v2:
> * Rebased onto qemu.git/master
> * Added comment explaining how the dataplane thread is restarted after
> draining [pbonzini]
>
> This series adds image format, QMP 'transation', and QMP 'block_resize'
> support
> to dataplane. This is
"Michael S. Tsirkin" writes:
> On Thu, Jul 11, 2013 at 12:52:56PM -0600, Eric Blake wrote:
>> On 07/11/2013 08:28 AM, Amos Kong wrote:
>> > Markus added some comments on old patchset, this patch contains
>> > some additional fixes, it's based on MST's PCI tree.
>> >
>> > * Fix typos (missed 1.6,
Amos Kong writes:
> Markus added some comments on old patchset, this patch contains
> some additional fixes, it's based on MST's PCI tree.
>
> * Fix typos (missed 1.6, NIC)
> * Don't initialize list point at its declaration
> * Always notify QMP client if mactable is changed
> * Returns NULL list
Cornelia Huck writes:
> The following changes since commit c3cb8e77804313e1be99b5f28a34a346736707a5:
>
> ioport: remove LITTLE_ENDIAN mark for portio (2013-07-12 14:37:47 -0500)
>
> are available in the git repository at:
>
> git://github.com/cohuck/qemu virtio-ccw-upstr
>
> for you to fetch
From: Mans Rullgard
The ARMv8 SEVL instruction is in the architectural hint space already
emulated as nop. This makes the decoding of SEVL explicit for clarity.
Signed-off-by: Mans Rullgard
Message-id: 1370606786-5650-3-git-send-email-m...@mansr.com
[PMM: added 'SEVL' to the TODO comment]
Sign
From: Peter Crosthwaite
Unimplemented registers in the cp15, CRn=0, opc1=0, CRm=0 space default
to aliasing the MIDR register. Set all registers in the space to access
MIDR by default.
Signed-off-by: Peter Crosthwaite
Message-id:
6127846712b7ad2727354a4f5e1d809451f1e859.1373429432.git.peter.cr
The A15 Versatile Express board can remap a variety of things at address
0. We don't currently emulate the Serial Configuration Controller which
is how the guest can control this remapping, but we can provide the
initial default mapping of the first flash device into this space.
In particular this
repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-arm-devs-20130715
for you to fetch changes up to b25a83f0538fceede15cba6cfd6ea0f1ffc9d777:
ARM/highbank: add support for Calxeda ECX-2000 / Midway (2013-07-15 16:25:57
+0100
From: Mans Rullgard
Signed-off-by: Mans Rullgard
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
target-arm/cpu.c |7 ++-
target-arm/cpu.h |1 +
target-arm/translate.c |1 +
3 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/target-arm/cpu.c
To enable VSS support in qemu-ga for Windows, header files included in
VSS SDK are required.
The VSS support is enabled by the configure option like below:
./configure --with-vss-sdk="/path/to/VSS SDK"
If the path is omitted, it tries to search the headers from default paths
and VSS support is e
From: Peter Crosthwaite
The if block detecting OMAP/StrongARM modifies the id_cp_reginfo
.access fields in place. So there is no need to replicate the call
to define_arm_cp_reg(). Dropped, and let the OMAP case fall through
to the normal behaviour after the in-place modification.
Signed-off-by:
The drqbmp field of struct soc_dma_s is a uint64_t; however several
places in the code attempt to set bits in it using "(1 << drq)",
which will fail if drq is large enough that the 1 bit gets shifted
off the top of a 32 bit integer. Change these to "(1ULL << drq)" so
that the promotion to 64 bit h
The CMOV feature bit (bit 15 of EDX) should affect availability of the
following instructions:
CMOVcc (0F 40 -> 0F 4F)
FCMOVcc (DA C0 -> DA DF and DB C0 -> DB DF)
FCOMI family (DB E8 -> DB F7 and DF E8 -> DF F7)
HTH
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From: Andre Przywara
To allow the modelling of machines similar to Calxeda Highbank,
introduce a parameter to the init function and call it from a
wrapper. This allows to tweak the definition for individual machines
later on.
Signed-off-by: Andre Przywara
Message-id: 1373026897-12085-2-git-send
Add a cast to avoid potentially shifting into the sign bit of
a signed value, which is undefined behaviour in C.
(Detected with clang's -fsanitize=undefined.)
Signed-off-by: Peter Maydell
Message-id: 1372341831-4264-1-git-send-email-peter.mayd...@linaro.org
---
hw/sd/pl181.c |2 +-
1 file c
707a5:
ioport: remove LITTLE_ENDIAN mark for portio (2013-07-12 14:37:47 -0500)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20130715-1
for you to fetch changes up to 82a3a11897308b606120f7235001e87809708f85:
target-arm:
guest-fsfreeze-freeze command can take longer than 3 seconds when heavy
disk I/O is running. To avoid unexpected timeout, this changes the timeout
to 60 seconds (timeout of pre-commit phase of VSS).
Signed-off-by: Tomoki Sekiyama
Reviewed-by: Paolo Bonzini
Reviewed-by: Laszlo Ersek
---
QMP/qem
Support guest-fsfreeze-freeze and guest-fsfreeze-thaw commands for Windows
guests. When fsfreeze command is issued, it calls the VSS requester to
freeze filesystems and applications. On thaw command, it again tells the VSS
requester to thaw them.
This also adds calling of initialize functions for
These functions help maintaining homogeneous formatting of error messages
with Windows error code and description (generated by
g_win32_error_message()).
Signed-off-by: Tomoki Sekiyama
---
include/qapi/error.h | 13 +
util/error.c | 35 +++
VSS SDK(*) setup.exe is only runnable on Windows. This adds a script
to extract VSS SDK headers on POSIX-systems using msitools.
* http://www.microsoft.com/en-us/download/details.aspx?id=23490
From: Paolo Bonzini
Signed-off-by: Paolo Bonzini
Signed-off-by: Tomoki Sekiyama
Reviewed-by: Laszlo
Add configuration for C++ compiler in configure and Makefiles.
The C++ compiler is choosed as following:
- ${CXX}, if it is specified.
- ${cross_prefix}g++, if ${cross_prefix} is specified.
- Otherwise, c++ is used.
Currently, usage of C++ language is only for access to Windows VSS
using COM+ s
Register QGA VSS provider library into Windows when qemu-ga is installed as
Windows service ('-s install' option). It is deregistered when the service
is uninstalled ('-s uninstall' option).
Signed-off-by: Tomoki Sekiyama
---
qga/main.c | 10 +-
qga/vss-win32.c | 25
Enable checkpatch.pl to apply the same checks as C source files for
C++ files with .cpp extensions. It also adds some exceptions for C++
sources to suppress errors for:
- <> used in C++ template arguments (e.g. template )
- :: used to represent namespaces (e.g. SomeClass::method())
- : used
Add c++ keywords to avoid errors in compiling with c++ compiler.
This also renames class member of PciDeviceInfo to q_class.
Signed-off-by: Tomoki Sekiyama
Reviewed-by: Laszlo Ersek
---
hmp.c |2 +-
hw/pci/pci.c|2 +-
scripts/qapi.py | 12 +++-
3 files changed, 1
Hi,
This is v7 of patch series to add fsfreeze for Windows qemu-guest-agent.
changes from v7:
- Fix COM initialization issue for Windows service thread (patch 07/10)
v6: http://lists.nongnu.org/archive/html/qemu-devel/2013-07/msg01788.html
* Description
In Windows, VSS (Volume Shadow Copy S
g_hash_table_get_keys() was only introduced in glib 2.14, and we're
still targeting a minimum version of 2.12. Rewrite the offending
code (introduced in commit 721fae1) to use g_hash_table_foreach()
to build the list of keys.
Signed-off-by: Peter Maydell
Tested-by: Laurent Desnogues
Tested-by:
From: Peter Crosthwaite
Allow for defining const opaque data in ARM CP register definitions by
setting .opaque = foo. If non null opaque is passed into
define_one_arm_cp_reg_with_opaque then that opaque will take
precedence, otherwise if null opaque is passed, the original opaque
data will be use
LPAE CPUs have more potentially valid bits in the TTBCR, and so the
simple masking out of invalid bits is no longer sufficient to obtain
the base address width field of the register, which is what we use to
precalculate c2_mask and c2_base_mask. Explicitly extract the
relevant register field rathe
From: Mans Rullgard
This adds support for the ARMv8 load acquire/store release instructions.
Since qemu does nothing special for memory barriers, these can be
emulated like their non-acquire/release counterparts.
Signed-off-by: Mans Rullgard
Signed-off-by: Peter Maydell
---
target-arm/transla
On 04/07/13 22:52, Olivier Danet wrote:
The bug was introduced in Linux 3.8
Here is a patch for swift, there are also issues in hypersparc.S,
viking.S, tsunami.S ...:
==
diff -up linux_prev/arch/sparc/mm/swift.S linux/arch
From: Peter Crosthwaite
commit 1db8b5efe0c2b5000e50691eea61264a615f43de introduced an issue
where QEMU would segfault if you have an unattached Cadence UART.
Fix by guarding the flush-on-reset logic on there being a qemu_chr
attachment.
Reported-by: Soren Brinkmann
Signed-off-by: Peter Crosthw
From: Andre Przywara
The Calxeda ECX-2000 chip (aka. Midway) is model-wise quite similar
to the Highbank. The most prominent difference is the Cortex-A15 CPU
core in it, together with the associated core peripherals.
Add a new ARM machine type called "midway".
Move the L2 cache controller device
On Mon, Jul 15, 2013 at 03:22:33PM +0200, Laszlo Ersek wrote:
> On 07/10/13 15:51, Michael S. Tsirkin wrote:
>
> > @@ -697,7 +703,12 @@ static void rom_reset(void *unused)
> > if (rom->data == NULL) {
> > continue;
> > }
> > -cpu_physical_memory_write_rom(rom
The a15mpcore device claims that its default value for num-irq
is the number of interrupts used by the A15MP in the vexpress-a15
board. However that chip has 128 external interrupts, not 64.
Since there is only one A15 based model in QEMU currently, we
can fix this by simply changing the default va
Il 15/07/2013 17:20, Andreas Färber ha scritto:
> We have some ugly include chains - yes, it shouldn't be here forever.
> Just like the qemu/log.h situation is pretty unsatisfactory (I wouldve
> liked to place log_cpu_state() into qom/cpu.h but it depends in
> qemu-common.h and even ignoring that d
Please note that two features: acpi table generation and pci bridge
hotplug support - intended for 1.6 have been posted but not yet
committed.
Feature pages and feature description can be found in the wiki.
I'm addressing review comments for these two patchsets.
While they are large they are also
> Incidentally, if you're using KVM acceleration then these
> instructions won't fault in that setup because the host CPU
> hardware doesn't provide a means for trapping them.
This I already understood, and we made sure that we were running with
the TCG backend.
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On 15 July 2013 16:35, Jonathan Morton <1201...@bugs.launchpad.net> wrote:
>> Actually, we do do testing of feature bits for things like SSE2,
> 3DNow!, and so on -- it looks like we just missed cmov.
>
> That's encouraging to hear - I hadn't specifically tested for the
> behaviour in the other cas
The following changes since commit c3cb8e77804313e1be99b5f28a34a346736707a5:
ioport: remove LITTLE_ENDIAN mark for portio (2013-07-12 14:37:47 -0500)
are available in the git repository at:
git://github.com/cohuck/qemu virtio-ccw-upstr
for you to fetch changes up to bf72d89f0a8fb27a6bfde1a6
From: Dominik Dingel
Add property x-data-plane to virtio-ccw-blk devices.
Signed-off-by: Dominik Dingel
Signed-off-by: Cornelia Huck
---
hw/s390x/virtio-ccw.c |3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/s390x/virtio-ccw.c b/hw/s390x/virtio-ccw.c
index e744957..8835bd4 100644
> Actually, we do do testing of feature bits for things like SSE2,
3DNow!, and so on -- it looks like we just missed cmov.
That's encouraging to hear - I hadn't specifically tested for the
behaviour in the other cases I described, just extrapolated.
Is there a good chance that the CMOV thing will
Il 15/07/2013 17:06, Andreas Färber ha scritto:
> Am 15.07.2013 16:43, schrieb Paolo Bonzini:
>> Il 15/07/2013 15:40, Andreas Färber ha scritto:
>>> Originally Paolo and me had implemented QOM realize at Object level.
>>> Paolo's goal was to set realized = true on /machine and it propagating from
>
Hi Baiqing,
Thank you for reporting the problem.
I found a initialization issue for the Windows service thread in the v6
patch.
The patch attached should fix the problem.
I will submit the v7 patch including this soon.
Thanks,
Tomoki Sekiyama
On 7/15/13 5:23 , "Libaiqing" wrote:
>Hi tomoki,
From: Alexey Kardashevskiy
At present, the savevm / migration support for the pseries machine will not
work when KVM is enabled. That's because KVM manages the guest's hash page
table in the host kernel, so qemu has no visibility of it. This patch
fixes this by using new kernel interfaces to ex
From: David Gibson
This adds the necessary pieces to implement savevm / migration for the
pseries machine. The most complex part here is migrating the hash
table - for the paravirtualized pseries machine the guest's hash page
table is not stored within guest memory, but externally and the guest
From: David Gibson
This adds the necessary support for saving the state of the PAPR virtual
PCI host bridge (or host bridges).
Signed-off-by: David Gibson
Reviewed-by: Anthony Liguori
---
hw/ppc/spapr_pci.c | 49 +
include/hw/pci-host/spapr
On 5 July 2013 13:21, Andre Przywara wrote:
> While the Calxeda Midway part is actually a bit more than a "Highbank
> with A15s", for QEMU's purposes this view is sufficient.
> So refactor the Highbank initialization to allow a very similar
> machine and add the necessary changes to support the ne
>From Ben:
Basically, in HW the layout of the interrupt network is:
- One ICP per processor thread (the "presenter"). This contains the
registers to fetch a pending interrupt (ack), EOI, and control the
processor priority.
- One ICS per logical source of interrupts (ie, one
** Changed in: qemu
Assignee: (unassigned) => Don Koch (dkoch-r)
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https://bugs.launchpad.net/bugs/1187529
Title:
Devices on PCI bridge stop working when live-migrated
Status in Q
Am 15.07.2013 16:56, schrieb Paolo Bonzini:
> Il 16/06/2013 17:57, Andreas Färber ha scritto:
>> Move it to qom/cpu.h.
>
> Hmm, why move it to qom/cpu.h? Isn't it an implementation detail that
> there is a current CPU?
We have some ugly include chains - yes, it shouldn't be here forever.
Just li
This series is based on Alexey's series:
spapr: migration, pci, msi, power8
Which in turn was based on work by David Gibson.
I've removed the bits not related to migration and made the
following changes:
1) QOMify TCE tables and XICS
2) Do everything in terms of VMStateDescriptions
3) Fi
From: David Gibson
This patch adds the necessary VMStateDescription information to support
savevm/loadvm for the spapr_llan (PAPR logical lan) device.
Signed-off-by: David Gibson
Reviewed-by: Anthony Liguori
---
hw/net/spapr_llan.c | 24 ++--
1 file changed, 22 insertions(
Hard freeze is two weeks away.
http://wiki.qemu.org/Planning/1.6
Regards,
Anthony Liguori
From: Paolo Bonzini
The next patch will change qemu/tls.h to support more platforms, but at
some performance cost. Declare current_cpu directly instead of using
the tls.h abstractions.
Signed-off-by: Paolo Bonzini
---
Paolo may have further improvements for these patches. This is my local
ve
From: Paolo Bonzini
Fast TLS is not available on some platforms, but it is always nice to
use it. This wrapper implementation falls back to pthread_get/setspecific
on POSIX systems that lack __thread, but uses the dynamic linker's TLS
support on Linux and Windows.
The user shall call tls_alloc_
From: David Gibson
This patch adds helpers to allow PAPR VIO devices to save state common
to all VIO devices during savevm.
Signed-off-by: David Gibson
Reviewed-by: Anthony Liguori
---
hw/ppc/spapr_vio.c | 20
include/hw/ppc/spapr_vio.h | 5 +
2 files changed
From: David Gibson
This patch adds the necessary support for saving the state of the PAPR VIO
virtual SCSI device. This also saves and restores active SCSI requests.
[aik: implemented vscsi_req save/restore]
Signed-off-by: Alexey Kardashevskiy
Cc: David Gibson
---
hw/scsi/spapr_vscsi.c | 82 +
From: Alexey Kardashevskiy
The savevm code for the powerpc cpu emulation is currently based around
the old register_savevm() rather than register_vmstate() method. It's also
rather broken, missing some important state on some CPU models.
This patch completely rewrites the savevm for target-ppc,
From: Alexey Kardashevskiy
The patch reimplements handling of indirect requests in order to
simplify upcoming live migration support.
- all pointers (except SCSIRequest*) were replaces with integer
indexes and offsets;
- DMA'ed srp_direct_buf kept untouched (ie. BE format);
- vscsi_fetch_desc() i
From: David Gibson
This patch adds the necessary VMStateDescription information to support
savevm/loadvm for the spapr_tty (PAPR logical serial) device.
Signed-off-by: David Gibson
Reviewed-by: Anthony Liguori
---
hw/char/spapr_vty.c | 16
1 file changed, 16 insertions(+)
di
Model TCE tables as a device that's hooked up as a child object to
the owner. Besides the code cleanup, we get a few nice benefits:
1) free actually works now (it was dead code before)
2) the TCE information is visible in the device tree
3) we can expose table information as properties such tha
Il 16/06/2013 17:57, Andreas Färber ha scritto:
> Move it to qom/cpu.h.
Hmm, why move it to qom/cpu.h? Isn't it an implementation detail that
there is a current CPU?
Paolo
> Signed-off-by: Andreas Färber
> ---
> cpu-exec.c | 13 +++--
> cpus.c | 29 ++
Paolo Bonzini writes:
> Il 08/07/2013 20:39, Anthony Liguori ha scritto:
>> Alexey Kardashevskiy writes:
>>
>>> From: David Gibson
>>>
>>> This patch adds the necessary VMStateDescription information to save the
>>> state of PAPR TCE tables (that is, the PAPR specified IOMMU).
>>>
>>> Signed-o
Am 15.07.2013 16:43, schrieb Paolo Bonzini:
> Il 15/07/2013 15:40, Andreas Färber ha scritto:
>> Originally Paolo and me had implemented QOM realize at Object level.
>> Paolo's goal was to set realized = true on /machine and it propagating from
>> there on. This series now implements {realize,unrea
Hi,
Please find the status of the upstream testing:
Kernel : 3.10.0-rc5+
Qemu : 1.5.50
Libvirt : 1.0.6
Bugs filed in this week : 5
Qemu Bugs in Launchpad :
---
Bug# 1199416 - Hot-add qcow2 [virtio-scsi] devices doesn't work in
SlLES-11-SP2guest
https://bugs
On 15 July 2013 15:17, Jonathan Morton <1201...@bugs.launchpad.net> wrote:
> We encountered a bug in another package that caused it to include CMOV
> instructions when targetting i486, resulting in an inability to run the
> package on real i486 and i586 hardware. We then attempted to use QEMU
> to
Alexey Kardashevskiy writes:
> On 07/13/2013 06:03 PM, David Gibson wrote:
>> On Fri, Jul 12, 2013 at 05:37:19PM +1000, Alexey Kardashevskiy wrote:
>>> sPAPR PHB emulates IO ports on PCI via a special memory region which
>>> routes all reads/writes further via cpu_in*/cpu_out* which are eventuall
On 7 July 2013 19:25, Andreas Färber wrote:
> vaddr is to target_ulong what uintmax_t is to unsigned int.
>
> Its purpose is to allow turning per-target functions with target_ulong
> arguments into CPUClass hooks.
>
> Suggested-by: Peter Maydell
> Signed-off-by: Andreas Färber
> ---
> include/q
virtio-blk data plane only worked with -drive format=raw,aio=native. It
used raw_get_aio_fd() to fetch the file descriptor from raw-posix. This
was a layering violation and is no longer necessary now that virtio-blk
data plane uses the QEMU block layer.
Signed-off-by: Stefan Hajnoczi
---
block
virtio-blk data plane used a custom Linux AIO request queue called
"ioq". Now that virtio-blk data plane uses the QEMU block layer we can
drop ioq.
Signed-off-by: Stefan Hajnoczi
---
hw/block/dataplane/Makefile.objs | 2 +-
hw/block/dataplane/ioq.c | 117 --
Use the QEMU block layer instead of custom Linux AIO code. A couple of
changes are necessary to make request processing work in this new
environment:
1. Replace ioq_*() calls with bdrv_aio_*(). We finally support
asynchronous flush since we get it for free from the QEMU block
layer!
2. Ad
Timers only work in the main loop. This means threads running their own
AioContext cannot use I/O throttling for now.
Signed-off-by: Stefan Hajnoczi
---
block.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/block.c b/block.c
index 26644ec..daf5717 100644
--- a/block.c
+++ b/block.c
@
Each block/raw-posix.c BlockDriverState has a struct qemu_laio_state
that holds the Linux AIO context. Currently the EventNotifier is
assigned to the main loop.
In order to use block/linux-aio.c from other threads/event loops, we
need to assign the EventNotifier to the current event loop. This p
qemu_bh_new() and several other functions use qemu_aio_context, the
global QEMU main loop AioContext. Now that we have introduced threads
with their own AioContext and a thread-local AioContext pointer, convert
qemu_bh_new() and friends to use the thread-local AioContext pointer.
qemu_bh_new() no
Associating a BlockDriverState with a single AioContext is not flexible
enough. Once we make BlockDriverState thread-safe, it will be possible
to call bdrv_*() functions from multiple event loops.
Use the thread-local AioContext pointer instead of
bdrv_get_aio_context().
Signed-off-by: Stefan Ha
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