Instantiate all [*] machines per target, so that they get a bit of test
coverage at all. This has proven helpful during QOM refactorings.
[*] ppcemb target contains some non-working non-embedded machines, and
ppc405 CPUs are not available there either.
i386 and x86_64 do not cover pc*-x.y or
On Mon, Aug 05, 2013 at 10:45:31AM +0200, Andreas Färber wrote:
Am 05.08.2013 00:04, schrieb Aurélien Jarno:
On Mon, Jul 29, 2013 at 10:35:31PM +0200, Stefan Weil wrote:
Am 27.07.2013 22:58, schrieb Stefan Weil:
Am 27.07.2013 22:43, schrieb Andreas Färber:
Am 27.07.2013 21:37, schrieb
@Sam,
I have the license now, but haven't had a chance to reproduce yet,
sorry. It's on my list.
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/685096
Title:
USB Passthrough not working for
Signed-off-by: Andreas Färber afaer...@suse.de
---
hw/ppc/ppc405_uc.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 290f71a..5fc330b 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -30,15 +30,15 @@
Am 05.08.2013 00:06, schrieb Aurelien Jarno:
On Sun, Aug 04, 2013 at 02:03:20PM +0200, Andreas Färber wrote:
Am 04.08.2013 00:02, schrieb Aurelien Jarno:
Now that this code path is not triggered anymore during the tests,
revert commit b332d24a8e1290954029814d09156b06ede358e2. Booting a MIPS
Am 05.08.2013 15:31, schrieb Aurélien Jarno:
On Mon, Aug 05, 2013 at 10:45:31AM +0200, Andreas Färber wrote:
Am 05.08.2013 00:04, schrieb Aurélien Jarno:
On Mon, Jul 29, 2013 at 10:35:31PM +0200, Stefan Weil wrote:
Am 27.07.2013 22:58, schrieb Stefan Weil:
Am 27.07.2013 22:43, schrieb Andreas
On Mon, Aug 05, 2013 at 08:28:50AM -0500, Anthony Liguori wrote:
Daniel P. Berrange berra...@redhat.com writes:
On Mon, Aug 05, 2013 at 12:18:10PM +0100, Peter Maydell wrote:
This patch series adds a 'virt' platform which uses the
kernel's mach-virt (fully device-tree driven) support
to
Andreas Färber a écrit :
[snip]
Have you tested Jan's patches limiting the new unassigned read value -1
to PIO?
I have tried this patches, and they don't fix the problem.
Too bad. So what do you propose? Restoring #ifdef and using
empty_slot_init() have been suggested so far, any other
In kvm mode, vm_clock may be read outside BQL.
Not just in KVM mode (we will be able to use dataplane with TCG sooner
or later), actually.
Otherwise looks good!
Paolo
This will make
timers_state --the foundation of vm_clock exposed to race condition.
Using private lock to protect it.
Signed-off-by: Andreas Färber afaer...@suse.de
---
hw/m68k/an5206.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/m68k/an5206.c b/hw/m68k/an5206.c
index 0c03a87..abf7d1c 100644
--- a/hw/m68k/an5206.c
+++ b/hw/m68k/an5206.c
@@ -12,6 +12,7 @@
#include hw/loader.h
#include elf.h
On Mon, Aug 05, 2013 at 02:02:54PM +0100, Peter Maydell wrote:
On 5 August 2013 13:49, Daniel P. Berrange berra...@redhat.com wrote:
On x86, we've long had versioned machine names, so that we can
make changes in future QEMU releases without breaking guest ABI
compatibility. AFAICT, the
On Mon, Aug 05, 2013 at 03:53:08PM +0200, Hervé Poussineau wrote:
Andreas Färber a écrit :
[snip]
Have you tested Jan's patches limiting the new unassigned read value -1
to PIO?
I have tried this patches, and they don't fix the problem.
Too bad. So what do you propose? Restoring #ifdef
Signed-off-by: Andreas Färber afaer...@suse.de
---
hw/sh4/shix.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/hw/sh4/shix.c b/hw/sh4/shix.c
index 84dd666..66cbea4 100644
--- a/hw/sh4/shix.c
+++ b/hw/sh4/shix.c
@@ -50,7 +50,6 @@ static void shix_init(QEMUMachineInitArgs *args)
if
Daniel P. Berrange berra...@redhat.com writes:
On Mon, Aug 05, 2013 at 08:28:50AM -0500, Anthony Liguori wrote:
Daniel P. Berrange berra...@redhat.com writes:
On Mon, Aug 05, 2013 at 12:18:10PM +0100, Peter Maydell wrote:
This patch series adds a 'virt' platform which uses the
kernel's
Hi!
On Sun, 28 Jul 2013 02:39:23 +, Petar Jovanovic
petar.jovano...@imgtec.com wrote:
Will there be an update to this patch?
| Switch to 64-bit FPU only for n32 and n64 ABIs, but not o32. Fixup for
| commit 68473f15d4c9948986618f63828825beafcaf1cf.
| [...]
My patch has to be reworked per
On 5 August 2013 15:07, Aurélien Jarno aurel...@aurel32.net wrote:
On Mon, Aug 05, 2013 at 03:53:08PM +0200, Hervé Poussineau wrote:
Another idea (not tested): override the
CPUClass-do_unassigned_level on board level, to only raise IBE and
no DBE.
This sounds like a bit of a layering
On 08/05/2013 10:19 AM, Laszlo Ersek wrote:
While the machine is paused, in guest_phys_blocks_append() we register a
one-shot MemoryListener, solely for the initial collection of the valid
guest-physical memory ranges that happens at client registration time.
For each range that is reported to
Adopt error_report().
Signed-off-by: Andreas Färber afaer...@suse.de
---
hw/arm/armv7m.c | 25 ++---
1 file changed, 14 insertions(+), 11 deletions(-)
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
index 82d36fb..ddbaf8c 100644
--- a/hw/arm/armv7m.c
+++ b/hw/arm/armv7m.c
@@
Signed-off-by: Andreas Färber afaer...@suse.de
---
hw/sparc/leon3.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c
index 5ef282f..1d60cb7 100644
--- a/hw/sparc/leon3.c
+++ b/hw/sparc/leon3.c
@@ -26,6 +26,7 @@
#include hw/ptimer.h
On Mon, Aug 5, 2013 at 2:10 PM, Gonglei (Arei) arei.gong...@huawei.com wrote:
Hi,
-Original Message-
From: Gonglei (Arei)
Sent: Tuesday, July 30, 2013 10:01 AM
To: 'Pasi Kärkkäinen'
Cc: Gerd Hoffmann; Andreas Färber; Hanweidong; Luonengjun;
qemu-devel@nongnu.org;
Signed-off-by: Andreas Färber afaer...@suse.de
---
hw/arm/exynos4_boards.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
index 7c90b2d..0be5f8c 100644
--- a/hw/arm/exynos4_boards.c
+++ b/hw/arm/exynos4_boards.c
@@ -22,6
Replacing the assert() with more user-friendly error handling is left
for a follow-up.
Signed-off-by: Andreas Färber afaer...@suse.de
---
hw/unicore32/puv3.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/unicore32/puv3.c b/hw/unicore32/puv3.c
index 5ff0dc9..0d84cd9 100644
---
From: Gerd Hoffmann kra...@redhat.com
pci_bridge_write_config() was not being used.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Gerd Hoffmann kra...@redhat.com
Signed-off-by: Andreas Färber afaer...@suse.de
---
hw/pci-bridge/i82801b11.c | 1 +
1 file changed, 1 insertion(+)
diff --git
Hello Michael,
This mini-series cleans up Gerd's commit message and adds the generalization on
top.
Both look safe for 1.6 to me; doing it in two steps not only allows to record
Gerd's authorship but allows to cherry-pick his patch for 1.5 while mine is
1.6+.
Regards,
Andreas
Gerd's v1 - v2:
Set PCIDeviceClass::is_bridge as well as PCIDeviceClass::config_write(),
PCIDeviceClass::exit() and DeviceClass::reset() defaults directly for
TYPE_PCI_BRIDGE (complements f055e96bd4311d287c0e03faec02a1bdbc351925).
This avoids another pci_bridge_config_write() missing somewhere, unless
explicitly
Signed-off-by: Andreas Färber afaer...@suse.de
---
hw/arm/omap_sx1.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
index 05b0353..d9bd8d6 100644
--- a/hw/arm/omap_sx1.c
+++ b/hw/arm/omap_sx1.c
@@ -32,6 +32,7 @@
#include hw/arm/arm.h
Adopt error_report() while at it.
Signed-off-by: Andreas Färber afaer...@suse.de
---
hw/block/tc58128.c | 10 ++
hw/sh4/shix.c | 9 +
2 files changed, 11 insertions(+), 8 deletions(-)
diff --git a/hw/block/tc58128.c b/hw/block/tc58128.c
index a3929d4..728f1c3 100644
---
On 08/05/2013 04:36 PM, Andreas Färber wrote:
Set PCIDeviceClass::is_bridge as well as PCIDeviceClass::config_write(),
PCIDeviceClass::exit() and DeviceClass::reset() defaults directly for
TYPE_PCI_BRIDGE (complements f055e96bd4311d287c0e03faec02a1bdbc351925).
This avoids another
Am 01.08.2013 um 05:23 hat Jeff Cody geschrieben:
This adds the ability to update the headers in a VHDX image, including
generating a new MS-compatible GUID.
As VHDX depends on uuid.h, VHDX is now a configurable build option. If
VHDX support is enabled, that will also enable uuid as well.
Signed-off-by: Andreas Färber afaer...@suse.de
---
hw/m68k/mcf5208.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/m68k/mcf5208.c b/hw/m68k/mcf5208.c
index 9cf000f..14fecc4 100644
--- a/hw/m68k/mcf5208.c
+++ b/hw/m68k/mcf5208.c
@@ -10,6 +10,7 @@
#include qemu/timer.h
#include
On Mon, Aug 05, 2013 at 01:42:32PM +0200, Kevin Wolf wrote:
Am 01.08.2013 um 05:23 hat Jeff Cody geschrieben:
This adds the ability to update the headers in a VHDX image, including
generating a new MS-compatible GUID.
As VHDX depends on uuid.h, VHDX is now a configurable build option.
On Mon, Aug 05, 2013 at 04:45:02PM +0200, Kevin Wolf wrote:
Am 01.08.2013 um 05:23 hat Jeff Cody geschrieben:
This adds the ability to update the headers in a VHDX image, including
generating a new MS-compatible GUID.
As VHDX depends on uuid.h, VHDX is now a configurable build option.
On 08/03/2013 01:32 PM, Laine Stump wrote:
1) Is this difference intentional, or a bug?
The vga simply goes into the first free slot. That happens to be #2
with i440fx and #1 with q35.
It sounds like it's a safe bet to assume that -vga will put the device
on slot 2 for pc machinetypes
Am 01.08.2013 um 05:23 hat Jeff Cody geschrieben:
This adds the ability to update the headers in a VHDX image, including
generating a new MS-compatible GUID.
As VHDX depends on uuid.h, VHDX is now a configurable build option. If
VHDX support is enabled, that will also enable uuid as well.
Hi,
However, unlike PC, I'd like to do linear versioning and avoid bumping
at every release.
IOW, spapr-1, spapr-2, spapr-3, etc.
I think virt ought to try to do the same.
Any particular reason why ? I kind of like the clarity of having the
version match the release version. Avoids
-Original Message-
From: dunl...@gmail.com [mailto:dunl...@gmail.com] On Behalf Of George
Dunlap
Sent: Monday, August 05, 2013 10:28 PM
To: Gonglei (Arei)
Cc: xen-de...@lists.xen.org; qemu-devel@nongnu.org; Anthony PERARD;
Stefano Stabellini
Subject: Re: [Xen-devel] FW: Cirrus VGA
On 07/28/13 08:35, Paolo Bonzini wrote:
This is quite handy to debug softmmu targets.
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
memory.c | 5 +
trace-events | 4
2 files changed, 9 insertions(+)
diff --git a/memory.c b/memory.c
index 1494e95..ac6f3c6 100644
---
On Mon, Aug 05, 2013 at 04:36:40PM +0200, Andreas Färber wrote:
From: Gerd Hoffmann kra...@redhat.com
pci_bridge_write_config() was not being used.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Gerd Hoffmann kra...@redhat.com
Signed-off-by: Andreas Färber afaer...@suse.de
Acked-by: Michael
On Mon, Aug 05, 2013 at 12:33:14PM +0200, Gerd Hoffmann wrote:
On 08/05/13 11:45, Andreas Färber wrote:
Am 05.08.2013 10:50, schrieb Gerd Hoffmann:
Signed-off-by: Gerd Hoffmann kra...@redhat.com
---
hw/pci-bridge/i82801b11.c |1 +
1 file changed, 1 insertion(+)
diff --git
On Mon, Aug 05, 2013 at 05:05:36PM +0200, Kevin Wolf wrote:
Am 01.08.2013 um 05:23 hat Jeff Cody geschrieben:
This adds the ability to update the headers in a VHDX image, including
generating a new MS-compatible GUID.
As VHDX depends on uuid.h, VHDX is now a configurable build option.
On 08/05/2013 07:00 AM, Stefan Hajnoczi wrote:
Filter out the QEMU monitor version banner so that tests do not break
when the QEMU version number is changed.
Signed-off-by: Stefan Hajnoczi stefa...@redhat.com
---
+++ b/tests/qemu-iotests/common.filter
@@ -155,7 +155,8 @@ _filter_qemu_io()
On 08/05/2013 05:18 PM, Don Slutz wrote:
diff --git a/trace-events b/trace-events
index 002df83..3e0dd74 100644
--- a/trace-events
+++ b/trace-events
@@ -1165,6 +1165,10 @@ kvm_vm_ioctl(int type, void *arg) type %d, arg
%p
kvm_vcpu_ioctl(int cpu_index, int type, void *arg) cpu_index %d,
type
On 07/28/2013 02:35 PM, Paolo Bonzini wrote:
The I/O port variant of fw_cfg is used by sparc64, which is a big-endian
machine.
Firmware swaps bytes before sending them to fw_cfg, so we need to unswap them in
the device.
This is only used on sparc64 and on (little-endian) x86, so it does not
Am 05.08.2013 16:41, schrieb Paolo Bonzini:
On 08/05/2013 04:36 PM, Andreas Färber wrote:
Set PCIDeviceClass::is_bridge as well as PCIDeviceClass::config_write(),
PCIDeviceClass::exit() and DeviceClass::reset() defaults directly for
TYPE_PCI_BRIDGE (complements
On 08/02/2013 12:33 AM, Paolo Bonzini wrote:
On 08/01/2013 05:24 AM, Brad wrote:
On 03/07/13 5:41 AM, Laszlo Ersek wrote:
On 07/03/13 10:58, Izumi Tsutsui wrote:
Fix following bugs in fallback implementation of counting semaphores
with mutex+condvar added in
Fix incorrect assumption that DSP and non-DSP versions of the following
instructions have the same encoding:
MULT, MULTU, MADD, MADDU, MSUB, MSUBU, MFHI, MFLO, MTHI, MTLO.
Correct the existing (non-DSP) instructions and add DSP equivalents.
Reference:
MIPS Architecture for Programmers Volume
On 08/05/2013 01:06 AM, Peter Maydell wrote:
+const char *exc = NULL;
+
+if (idx = 0 idx ARRAY_SIZE(excnames)) {
+exc = excnames[idx];
+}
+if (!exc) {
+exc = unknown;
+}
Silly test for null here.
const char *exc =
On 08/05/2013 01:06 AM, Peter Maydell wrote:
+const char *exc = NULL;
+
+if (idx = 0 idx ARRAY_SIZE(excnames)) {
+exc = excnames[idx];
+}
+if (!exc) {
+exc = unknown;
+}
Gah. Nevermind that last comment, I knew it was
Andreas Färber afaer...@suse.de writes:
Am 05.08.2013 00:06, schrieb Aurelien Jarno:
On Sun, Aug 04, 2013 at 02:03:20PM +0200, Andreas Färber wrote:
Am 04.08.2013 00:02, schrieb Aurelien Jarno:
Now that this code path is not triggered anymore during the tests,
revert commit
On 08/05/13 18:21, Paolo Bonzini wrote:
On 07/28/2013 02:35 PM, Paolo Bonzini wrote:
The I/O port variant of fw_cfg is used by sparc64, which is a
big-endian machine.
Firmware swaps bytes before sending them to fw_cfg, so we need to
unswap them in
the device.
This is only used on sparc64
On 08/05/2013 01:06 AM, Peter Maydell wrote:
The 'int' loglevel for recording interrupts and exceptions
requires support in the target-specific code. Implement
it for ARM. This improves debug logging in some situations
that were otherwise pretty opaque, such as when we fault
trying to execute
Public bug reported:
I have a problem with qemu when I attempt to configure qemu in a way that
AES-NI op-codes are enabled in quest. To do that, I have to configure qemu
to emulate a recent CPU. But that causes a problem, because with recent
CPUs, guest linux kernel code assumes that RDMSR of
Am 05.08.2013 18:43, schrieb Anthony Liguori:
Andreas Färber afaer...@suse.de writes:
Am 05.08.2013 00:06, schrieb Aurelien Jarno:
On Sun, Aug 04, 2013 at 02:03:20PM +0200, Andreas Färber wrote:
Am 04.08.2013 00:02, schrieb Aurelien Jarno:
Now that this code path is not triggered anymore
On Fri, Aug 02, 2013 at 11:16:56PM +0200, Andreas Färber wrote:
+#define IPOCTAL_GET_PARENT_CLASS(obj) \
+OBJECT_GET_PARENT_CLASS(obj, TYPE_IPOCTAL)
Hey, I cannot make it compile with the latest master:
hw/char/ipoctal232.c: In function ‘ipoctal_realize’:
hw/char/ipoctal232.c:544:5:
On Mon, Aug 05, 2013 at 05:17:30PM -, Jari Ruusu wrote:
Public bug reported:
I have a problem with qemu when I attempt to configure qemu in a way that
AES-NI op-codes are enabled in quest. To do that, I have to configure qemu
to emulate a recent CPU. But that causes a problem, because
Am 05.08.2013 17:16, schrieb Alberto Garcia:
On Fri, Aug 02, 2013 at 11:16:56PM +0200, Andreas Färber wrote:
+#define IPOCTAL_GET_PARENT_CLASS(obj) \
+OBJECT_GET_PARENT_CLASS(obj, TYPE_IPOCTAL)
Hey, I cannot make it compile with the latest master:
hw/char/ipoctal232.c: In function
Two patches that improve the code paths generated for syscalls;
generating an exception is silly, as we can directly chain the TBs.
One patch improving the code for the kernel itself, since the KSEG
superpage never changes. This idea probably applies to several
other targets as well.
One patch
The destination of the call_pal, and the cpu state, is very predictable;
there's no need for exiting the cpu loop.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-alpha/helper.h | 1 +
target-alpha/sys_helper.c | 12
target-alpha/translate.c | 25
This allows significantly more threading, and occasionally larger TBs,
when processing code for the kernel and PALcode.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-alpha/translate.c | 37 +
1 file changed, 29 insertions(+), 8 deletions(-)
With appropriate flushing when the PALBR changes, the target of
a CALL_PAL is so predictable we can chain to it.
Signed-off-by: Richard Henderson r...@twiddle.net
---
target-alpha/helper.h | 1 +
target-alpha/sys_helper.c | 5 +
target-alpha/translate.c | 20
3
Signed-off-by: Richard Henderson r...@twiddle.net
---
default-configs/alpha-softmmu.mak | 1 +
1 file changed, 1 insertion(+)
diff --git a/default-configs/alpha-softmmu.mak
b/default-configs/alpha-softmmu.mak
index bc07600..0810a2e 100644
--- a/default-configs/alpha-softmmu.mak
+++
Signed-off-by: Richard Henderson r...@twiddle.net
---
hw/alpha/typhoon.c | 202 +
1 file changed, 174 insertions(+), 28 deletions(-)
diff --git a/hw/alpha/typhoon.c b/hw/alpha/typhoon.c
index b7fb044..2450045 100644
--- a/hw/alpha/typhoon.c
+++
Instead of using a branch-call-branch sequence, arrange for a
call-branch sequence, using the ARM's conditional call insn.
This reduces the size of the slow-path within the TB, and makes
the GETPC_EXT implementation identical for TCG and not-TCG.
Signed-off-by: Richard Henderson r...@twiddle.net
Avoid a loop in the tlb_fill path; the fill will either succeed or
generate an exception.
Inline the slow_ld/st function; it was a complete copy of the main
helper except for the actual cross-page unaligned code, and the
compiler was inlining it anyway.
Add unlikely markers optimizing for the
clang warns that cpu_openrisc_load_kernel() can use 'entry' uninitialized:
hw/openrisc/openrisc_sim.c:69:9: error: variable 'entry' is used
uninitialized whenever '' condition is false
[-Werror,-Wsometimes-uninitialized]
if (kernel_filename !qtest_enabled()) {
^~~
Signed-off-by: Richard Henderson r...@twiddle.net
---
tcg/arm/tcg-target.c | 48 +++-
1 file changed, 43 insertions(+), 5 deletions(-)
diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index 6c4854d..9a14a20 100644
--- a/tcg/arm/tcg-target.c
+++
While these are rare from code that's been through the optimizer,
it's not uncommon within the tcg backend.
Signed-off-by: Richard Henderson r...@twiddle.net
---
tcg/ppc64/tcg-target.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/tcg/ppc64/tcg-target.c
This will enable the generation of tail-calls in a future patch.
Signed-off-by: Richard Henderson r...@twiddle.net
---
tcg/ppc64/tcg-target.c | 38 +++---
1 file changed, 19 insertions(+), 19 deletions(-)
diff --git a/tcg/ppc64/tcg-target.c
Now that AREG0 doesn't need to be a global register, non-conflicting
with the normal frame pointer, move it out of the middle of the set.
Signed-off-by: Richard Henderson r...@twiddle.net
---
tcg/ppc64/tcg-target.c | 4 ++--
tcg/ppc64/tcg-target.h | 2 +-
2 files changed, 3 insertions(+), 3
... before falling back to an indirect branch.
Signed-off-by: Richard Henderson r...@twiddle.net
---
tcg/ppc64/tcg-target.c | 31 ++-
1 file changed, 18 insertions(+), 13 deletions(-)
diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
index 94960a3..fce3e5d
About half of these patches are focused on reducing the number of
full 64-bit constants that need to be generated for addresses:
E.g. patch 5, looking through the function descriptor. If the
program is built --disable-pie, the elements of the function
descriptors are all 32-bit constants.
E.g.
This makes some bits easier to debug, being presented with a symbol
instead of a number inside gdb.
Signed-off-by: Richard Henderson r...@twiddle.net
---
tcg/ppc64/tcg-target.c | 273 +
1 file changed, 138 insertions(+), 135 deletions(-)
diff
There are no helpers that require the static chain.
Signed-off-by: Richard Henderson r...@twiddle.net
---
tcg/ppc64/tcg-target.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
index fce3e5d..ddc9581 100644
--- a/tcg/ppc64/tcg-target.c
+++
Previously we'd only handle 16-bit offsets from memory operand
without falling back to indexed, but it's easy to use ADDIS to
handle full 32-bit offsets.
This also lets us unify code that existed inline in tcg_out_op
for handling addition of large constants.
Signed-off-by: Richard Henderson
This results in significant code size reductions when manipulating
pointers into TCG's own data structures. E.g.
-OUT: [size=180]
+OUT: [size=132]
...
-xxx: li r2,16383 # goto_tb
-xxx: rldicr r2,r2,32,31
-xxx: orisr2,r2,39128
-xxx: ori r2,r2,376
-xxx: ldx
Remove conditionalization from tcg_target_reg_alloc_order, relying on
reserved_regs to prevent register allocation that shouldn't happen.
So R11 is now present in reg_alloc_order for __APPLE__, but also now
reserved.
Sort reg_alloc_order into call-saved, call-clobbered, and parameters.
This
On Mon, Aug 05, 2013 at 07:04:22PM +0300, Gleb Natapov wrote:
On Mon, Aug 05, 2013 at 06:03:34PM +0300, Michael S. Tsirkin wrote:
On Mon, Aug 05, 2013 at 12:20:44PM +0300, Gleb Natapov wrote:
On Mon, Aug 05, 2013 at 12:18:26PM +0300, Michael S. Tsirkin wrote:
On Mon, Aug 05, 2013 at
Less conditional compilation. Merge an add insn with the indexed
memory load insn. Load the tlb addend earlier. Avoid the address
update memory form.
Signed-off-by: Richard Henderson r...@twiddle.net
---
tcg/ppc64/tcg-target.c | 202 +++--
1 file
A handy value near the rest of the program's dynamic allocation.
We'll be able to use this value for constant address generation,
cross-TB references, and in the further future, constant pool refs.
Signed-off-by: Richard Henderson r...@twiddle.net
---
tcg/ppc64/tcg-target.c | 23
Signed-off-by: Richard Henderson r...@twiddle.net
---
configure | 2 +-
include/exec/exec-all.h | 4 +-
tcg/ppc64/tcg-target.c | 219 +++-
3 files changed, 146 insertions(+), 79 deletions(-)
diff --git a/configure b/configure
index
No point in splitting the write into 32-bit pieces.
Signed-off-by: Richard Henderson r...@twiddle.net
---
tcg/i386/tcg-target.c | 3 +--
tcg/tcg.c | 6 ++
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c
index
The existing code for the i386 ldst optimization does
jmps.+5
jmplrestart
jmplrestart
for the store path. This is idiotic to say the least. Especially
for x86_64, where we have available parameter registers. We replace
that with a simple
leaq
Use existing stack space for arguments; don't push/pop.
Use less ifdefs and more C ifs.
Signed-off-by: Richard Henderson r...@twiddle.net
---
tcg/i386/tcg-target.c | 159 +-
1 file changed, 68 insertions(+), 91 deletions(-)
diff --git
Allow the code that tcg generates to be less obtuse, passing in
the return address directly instead of computing it in the helper.
Maintain the old entrance point unchanged as an alternate entry point.
Signed-off-by: Richard Henderson r...@twiddle.net
---
include/exec/softmmu_defs.h | 46
Use a 7 byte lea before the ultimate 10 byte movq.
Signed-off-by: Richard Henderson r...@twiddle.net
---
tcg/i386/tcg-target.c | 19 ---
1 file changed, 16 insertions(+), 3 deletions(-)
diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c
index 841bd75..456bd9e 100644
---
Use the helper macros like TAI. Fix formatting.
Signed-off-by: Richard Henderson r...@twiddle.net
---
tcg/ppc64/tcg-target.c | 38 --
1 file changed, 16 insertions(+), 22 deletions(-)
diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
index
We were always doing an indirect jump anyway, and the sequence is
never longer than the 6 insns we were reserving for the direct jump.
Futher cleanups will reduce the length of the constant address load.
Signed-off-by: Richard Henderson r...@twiddle.net
---
include/exec/exec-all.h | 3 ++-
This patch series is a follow up to a previous RFC about converting functions
that dynamically yield execution depending on whether they are in executing in
a coroutine context or not to be explicitly statically annotated. This change
is necessary for the GSoC CPC project, but was also agreed in
From: Charlie Shepherd cs...@cam.ac.uk
Coroutine functions that can yield directly or indirectly should be annotated
with a coroutine_fn annotation. Add an explanation to that effect in
include/block/coroutine.h.
---
include/block/coroutine.h | 3 +++
1 file changed, 3 insertions(+)
diff --git
From: Charlie Shepherd cs...@cam.ac.uk
While it only really makes sense to call qemu_coroutine_self() in a coroutine
context, it cannot actually yield execution itself, so remove the coroutine_fn
annotation.
---
include/block/coroutine.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
This patch converts the .bdrv_open, .bdrv_file_open and .bdrv_create members of
struct BlockDriver
to be explicitly annotated as coroutine_fn, rather than yielding dynamically
depending on whether
they are executed in a coroutine context or not.
---
block.c | 16
This patch follows on from the previous one and converts some block layer
functions to be
explicitly annotated with coroutine_fn instead of yielding depending upon
calling context.
---
block.c | 235 ++
block/mirror.c| 4 +-
This patch updates the callers of block layer functions converted to explicit
coroutine_fn annotation in the previous patch.
---
block/bochs.c| 4 ++--
block/cloop.c| 4 ++--
block/cow.c | 8 +++
block/dmg.c | 8 +++
block/qcow.c
Discontinue the jump-around-jump-to-jump scheme, trading it for a single
immediate move instruction. The two extra jumps always consume 7 bytes,
whereas the immediate move is either 5 or 7 bytes depending on where the
code_gen_buffer gets located.
Signed-off-by: Richard Henderson
Loading 32-bit immediates instead of memory will be faster.
Don't attempt to generate full 64-bit immediates.
Signed-off-by: Richard Henderson r...@twiddle.net
---
tcg/ppc64/tcg-target.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/tcg/ppc64/tcg-target.c
On Mon, Jul 29, 2013 at 7:16 PM, Max Filippov jcmvb...@gmail.com wrote:
Hello Blue/Antony,
Please pull my current target-xtensa patch queue. There's a number of
assorted fixes, new testcase and performance optimization patch.
Changes since 2013-07-21: trivial rebase.
Ping?
The following
This patch adds a test for coroutine execution order in test-coroutine - this
catches a bug in the CPC coroutine implementation.
---
tests/test-coroutine.c | 54 ++
1 file changed, 54 insertions(+)
diff --git a/tests/test-coroutine.c
Some versions of clang will warn about adding integers to strings:
disas/i386.c:4753:23: error: adding 'char' to a string does not append
to the string [-Werror,-Wstring-plus-int]
oappend (%es: + intel_syntax);
~~~^~
disas/i386.c:4753:23: note: use array
Hi Charlie,
Many thanks for this patch series.
On Mon, Aug 05, 2013 at 08:44:05PM +0200, Charlie Shepherd wrote:
This patch converts the .bdrv_open, .bdrv_file_open and .bdrv_create members
of struct BlockDriver
to be explicitly annotated as coroutine_fn, rather than yielding dynamically
On 08/05/2013 07:36 AM, Andreas Färber wrote:
By comparison, having -alpha firmware just print Hello does not seem
all that useful to me... I wouldn't mind error'ing out without useful
arguments there.
One of these days I'll get around to adding the bits that let you say
boot on the PALcode
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