On Mon, 16 Dec 2013 10:41:13 +0800
Wenchao Xia wrote:
> 于 2013/12/14 7:50, Eric Blake 写道:
> > On 12/10/2013 10:48 PM, Wenchao Xia wrote:
> >> After this patch, hidden enum type BlockdevOptionsKind will not
> >> be generated, and other API can use enum BlockdevDriver.
> >>
> >> Signed-off-by: Wenc
On Wed, 11 Dec 2013 13:24:14 -0500
"Jason J. Herne" wrote:
> From: "Jason J. Herne"
>
> Add HMP cpu-add wrapper to allow cpu hot plugging via monitor.
>
> Signed-off-by: Jason J. Herne
Applied to the qmp branch, thanks.
> ---
> hmp-commands.hx | 13 +
> hmp.c | 10 +++
On 16.12.2013, at 21:51, Matthew Rosato wrote:
> Add memory information to read SCP info and add handlers for
> Read Storage Element Information, Attach Storage Element,
> Assign Storage and Unassign Storage.
>
> Signed-off-by: Matthew Rosato
> ---
> hw/s390x/sclp.c | 233
On Mon, 16 Dec 2013 21:50:53 +0200
"Michael S. Tsirkin" wrote:
> On Mon, Nov 25, 2013 at 03:39:13PM +0100, Igor Mammedov wrote:
> > On Thu, 21 Nov 2013 11:37:01 +0200
> > "Michael S. Tsirkin" wrote:
> >
> > > On Thu, Nov 21, 2013 at 03:38:44AM +0100, Igor Mammedov wrote:
> > > > - provides stat
On 12/16/13 21:38, Igor Mammedov wrote:
> On Mon, 16 Dec 2013 21:30:14 +0200
> "Michael S. Tsirkin" wrote:
>
>> On Fri, Dec 13, 2013 at 05:22:14PM +0100, Igor Mammedov wrote:
>>> .. and report range used by it to OSPM via _CRS.
>>> PRST is needed in SSDT since its base will depend on
>>> chipset
On Mon, 16 Dec 2013 22:13:30 +0100
Laszlo Ersek wrote:
> On 12/16/13 21:38, Igor Mammedov wrote:
> > On Mon, 16 Dec 2013 21:30:14 +0200
> > "Michael S. Tsirkin" wrote:
> >
> >> On Fri, Dec 13, 2013 at 05:22:14PM +0100, Igor Mammedov wrote:
> >>> .. and report range used by it to OSPM via _CRS.
On Mon, 16 Dec 2013 22:44:46 +0100
Laszlo Ersek wrote:
> On 12/16/13 21:38, Igor Mammedov wrote:
> > On Mon, 16 Dec 2013 21:30:14 +0200
> > "Michael S. Tsirkin" wrote:
> >
> >> On Fri, Dec 13, 2013 at 05:22:14PM +0100, Igor Mammedov wrote:
> >>> .. and report range used by it to OSPM via _CRS.
Am 16.12.2013 11:48, schrieb Gerd Hoffmann:
> From: Dave Airlie
>
> I've ported the SDL1.2 code over, and rewritten it to use the SDL2 interface.
>
> The biggest changes were in the input handling, where SDL2 has done a major
> overhaul, and I've had to include a generated translation file to get
On Mon, 16 Dec 2013 21:53:07 +0200
"Michael S. Tsirkin" wrote:
> On Fri, Dec 13, 2013 at 05:22:14PM +0100, Igor Mammedov wrote:
> > .. and report range used by it to OSPM via _CRS.
> > PRST is needed in SSDT since its base will depend on
> > chipset and will be dynamically set by QEMU.
> > Also m
On Tue, Dec 17, 2013 at 8:12 AM, Stefan Weil wrote:
> Am 16.12.2013 11:48, schrieb Gerd Hoffmann:
>> From: Dave Airlie
>>
>> I've ported the SDL1.2 code over, and rewritten it to use the SDL2 interface.
>>
>> The biggest changes were in the input handling, where SDL2 has done a major
>> overhaul,
On 12/16/13 22:59, Igor Mammedov wrote:
> On Mon, 16 Dec 2013 22:44:46 +0100
> Laszlo Ersek wrote:
>
>> On 12/16/13 21:38, Igor Mammedov wrote:
>>> On Mon, 16 Dec 2013 21:30:14 +0200
>>> "Michael S. Tsirkin" wrote:
>>>
On Fri, Dec 13, 2013 at 05:22:14PM +0100, Igor Mammedov wrote:
> ..
On Mon, 16 Dec 2013 23:22:56 +0100
Laszlo Ersek wrote:
> On 12/16/13 22:59, Igor Mammedov wrote:
> > On Mon, 16 Dec 2013 22:44:46 +0100
> > Laszlo Ersek wrote:
> >
> >> On 12/16/13 21:38, Igor Mammedov wrote:
> >>> On Mon, 16 Dec 2013 21:30:14 +0200
> >>> "Michael S. Tsirkin" wrote:
> >>>
> >>
On 16.12.2013, at 22:42, Alexander Graf wrote:
>
> On 16.12.2013, at 21:51, Matthew Rosato wrote:
>
[...]
>
>> +}
>> +}
>> +}
>> +sccb->h.response_code = cpu_to_be16(SCLP_RC_NORMAL_COMPLETION);
>> +}
>> +
>> static void sclp_execute(SCCB *sccb, uint64_t code)
>>
On Mon, Dec 16, 2013 at 8:36 AM, Amit Shah wrote:
> On (Mon) 09 Dec 2013 [22:10:12], Amos Kong wrote:
>> Bugzilla: https://bugs.launchpad.net/qemu/+bug/1253563
>>
>> We have a requests queue to cache the random data, but the second
>> will come in when the first request is returned, so we always
>
On Fri, Dec 13, 2013 at 4:44 AM, Igor Mammedov wrote:
> Currently it's possible to make PCIDevice not hotpluggable by using
> no_hotplug field of PCIDeviceClass. However it limits this
> only to PCI devices and prevents from generalizing hotplug code.
>
> So add similar field to DeviceClass so it
Igor Mammedov writes:
> changes since v2:
> * s/hotplugable/hotpluggable/
> * move hotplug check to an earlier patch:
> "qdev: add "hotpluggable" property to Device"
> --
> Refactor PCI specific hotplug API to a more generic/reusable one.
> Model it after SCSI-BUS like hotplug API replacing sin
On Tue, Dec 17, 2013 at 9:26 AM, Anthony Liguori wrote:
> Igor Mammedov writes:
>
>> changes since v2:
>> * s/hotplugable/hotpluggable/
>> * move hotplug check to an earlier patch:
>> "qdev: add "hotpluggable" property to Device"
>> --
>> Refactor PCI specific hotplug API to a more generic/reus
Laszlo Ersek writes:
> When qemu dies unexpectedly, for example in response to an explicit
> abort() call, or (more importantly) when an external signal is delivered
> to it that results in a coredump, sometimes it is useful to extract the
> guest vmcore from the qemu process' memory image. The g
On Thu, Nov 28, 2013 at 01:33:16PM +, Peter Maydell wrote:
> Split ARM KVM support code which is 32 bit specific out into its
> own file, which we only compile on 32 bit hosts. This will give
> us a place to add the 64 bit support code without adding lots of
> ifdefs to kvm.c.
>
> Signed-off-b
On Thu, Nov 28, 2013 at 01:33:17PM +, Peter Maydell wrote:
> The env->pstate field is a little odd since it doesn't strictly
> speaking represent an architectural register. However it's convenient
> for QEMU to use it to hold the various PSTATE architectural bits
> in the same format the archit
On Thu, Nov 28, 2013 at 01:33:19PM +, Peter Maydell wrote:
> Enable KVM if the host and target CPU are both aarch64. Note
> that host aarch64 + target arm is not valid for KVM acceleration:
> the 64 bit kernel does not support the ioctl interface for
> 32 bit CPUs. 32 bit VMs on 64 bit hosts ne
On Thu, Nov 28, 2013 at 01:33:18PM +, Peter Maydell wrote:
> From: "Mian M. Hamayun"
>
> Add the bare minimum set of functions needed for control of an
> AArch64 KVM vcpu:
> * CPU initialization
> * minimal get/put register functions which only handle the
>basic state of the CPU
>
> Si
On Thu, Nov 28, 2013 at 01:33:20PM +, Peter Maydell wrote:
> For AArch64 we will obviously require a different set of
> primary and secondary boot loader code fragments. However currently
> we hardcode the offsets into the loader code where we must write
> the entrypoint and other data into arm
On Thu, Nov 28, 2013 at 01:33:21PM +, Peter Maydell wrote:
> From: "Mian M. Hamayun"
>
> This commit adds support for booting a single AArch64 CPU by setting
> appropriate registers. The bootloader includes placehoders for Board-ID
> that are used to implement uniform indexing across differen
On Thu, Nov 28, 2013 at 01:33:22PM +, Peter Maydell wrote:
> Add a config for aarch64-softmmu; this enables building of this target.
> The resulting executable doesn't know about any 64 bit CPUs, but all
> the 32 bit CPUs and board models work.
>
> Signed-off-by: Peter Maydell
> ---
> defaul
On 16 December 2013 23:39, Christoffer Dall wrote:
> On Thu, Nov 28, 2013 at 01:33:17PM +, Peter Maydell wrote
>> --- a/target-arm/cpu.h
>> +++ b/target-arm/cpu.h
>> @@ -113,8 +113,13 @@ typedef struct CPUARMState {
>> /* Regs for A64 mode. */
>> uint64_t xregs[32];
>> uint64_t
On 16 December 2013 23:39, Christoffer Dall wrote:
> On Thu, Nov 28, 2013 at 01:33:18PM +, Peter Maydell wrote:
>> +ahcc->target = init.target;
>> +ahcc->dtb_compatible = "arm,arm-v7";
>
> arm,arm-v8 ?
Oops, yes, cut-n-pasto.
>
>> +
>> +kvm_arm_destroy_scratch_host_vcpu(fdarray)
On 16 December 2013 23:40, Christoffer Dall wrote:
> On Thu, Nov 28, 2013 at 01:33:20PM +, Peter Maydell wrote:
>> For AArch64 we will obviously require a different set of
>> primary and secondary boot loader code fragments. However currently
>> we hardcode the offsets into the loader code whe
I spent a couple hours today debugging a bug in an older branch of
libvirt (0.10.2) - one where libvirt only knew how to parse version 2
qcow2 images. Alas, that version of libvirt can be coerced into reading
the header of a random file under the assumption that it is qcow2 data,
and where it trie
On 16 December 2013 23:40, Christoffer Dall wrote:
> On Thu, Nov 28, 2013 at 01:33:21PM +, Peter Maydell wrote:
>> From: "Mian M. Hamayun"
>>
>> This commit adds support for booting a single AArch64 CPU by setting
>> appropriate registers. The bootloader includes placehoders for Board-ID
>> t
On 16 December 2013 23:40, Christoffer Dall wrote:
> On Thu, Nov 28, 2013 at 01:33:22PM +, Peter Maydell wrote:
>> Add a config for aarch64-softmmu; this enables building of this target.
>> The resulting executable doesn't know about any 64 bit CPUs, but all
>> the 32 bit CPUs and board models
On Mon, Dec 16, 2013 at 01:11:47PM +0100, Andreas Färber wrote:
> Am 16.12.2013 09:05, schrieb edgar.igles...@gmail.com:
> > From: "Edgar E. Iglesias"
> >
> > Signed-off-by: Edgar E. Iglesias
> > ---
> > cputlb.c|4 ++--
> > exec.c | 31 +++
When qemu dies unexpectedly, for example in response to an explicit
abort() call, or (more importantly) when an external signal is delivered
to it that results in a coredump, sometimes it is useful to extract the
guest vmcore from the qemu process' memory image. The guest vmcore might
help understa
On Fri, Dec 13, 2013 at 8:05 PM, Peter Maydell wrote:
> On 13 December 2013 03:19, Peter Crosthwaite
> wrote:
>> Why do we need blobs at all? Cant we just fix arm/boot to directly
>> setup the CPU state to the desired? Rather than complex blobs that
>> execute ARM instructions just manipulate the
On Mon, Dec 16, 2013 at 01:48:10PM +0100, Andreas Färber wrote:
> Am 16.12.2013 09:06, schrieb edgar.igles...@gmail.com:
> > From: "Edgar E. Iglesias"
> >
> > Signed-off-by: Edgar E. Iglesias
> > ---
> > exec.c |6 +++---
> > 1 file changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --g
At least libvirt 0.10.2 has a bug where it can be provoked
into attempting to search for extension headers (in particular,
the backing file format header) without first validating that
a particular file is qcow2 version 2. Fortunately, to date,
this probe always ends early when feeding a version 3
On 17 December 2013 00:34, Edgar E. Iglesias wrote:
> On Mon, Dec 16, 2013 at 01:11:47PM +0100, Andreas Färber wrote:
>> Why are you adding this field here rather than in CPUState alongside the
>> other field? This being a pointer I can't imagine problems for
>> non-softmmu, and I had posted patch
On Mon, Dec 16, 2013 at 01:54:11PM +0100, Andreas Färber wrote:
> Am 16.12.2013 09:05, schrieb edgar.igles...@gmail.com:
> > From: "Edgar E. Iglesias"
> >
> > Signed-off-by: Edgar E. Iglesias
> > ---
> > exec.c |5 +
> > 1 file changed, 5 insertions(+)
> >
> > diff --git a/exec.c b/exe
On Tue, Dec 17, 2013 at 10:54 AM, Peter Maydell
wrote:
> On 17 December 2013 00:34, Edgar E. Iglesias wrote:
>> On Mon, Dec 16, 2013 at 01:11:47PM +0100, Andreas Färber wrote:
>>> Why are you adding this field here rather than in CPUState alongside the
>>> other field? This being a pointer I can'
On 17 December 2013 00:52, Peter Crosthwaite
wrote:
> On Fri, Dec 13, 2013 at 8:05 PM, Peter Maydell
> wrote:
>> On 13 December 2013 03:19, Peter Crosthwaite
>> wrote:
>>> Why do we need blobs at all? Cant we just fix arm/boot to directly
>>> setup the CPU state to the desired? Rather than comp
On Tue, Dec 17, 2013 at 12:54:19AM +, Peter Maydell wrote:
> On 17 December 2013 00:34, Edgar E. Iglesias wrote:
> > On Mon, Dec 16, 2013 at 01:11:47PM +0100, Andreas Färber wrote:
> >> Why are you adding this field here rather than in CPUState alongside the
> >> other field? This being a poin
On Tue, Dec 17, 2013 at 10:58 AM, Peter Maydell
wrote:
> On 17 December 2013 00:52, Peter Crosthwaite
> wrote:
>> On Fri, Dec 13, 2013 at 8:05 PM, Peter Maydell
>> wrote:
>>> On 13 December 2013 03:19, Peter Crosthwaite
>>> wrote:
Why do we need blobs at all? Cant we just fix arm/boot to
On Mon, Dec 16, 2013 at 01:29:47PM +, Peter Maydell wrote:
> On 16 December 2013 12:46, Andreas Färber wrote:
> > Thanks for this series. I've been on vacation so couldn't review the
> > previous RFC yet... I'm not entirely happy with the way this is pushing
> > work to the machines here and w
On Mon, Dec 16, 2013 at 01:46:57PM +0100, Andreas Färber wrote:
> Hi Edgar,
>
> Am 16.12.2013 09:06, schrieb edgar.igles...@gmail.com:
> > From: "Edgar E. Iglesias"
> >
> > Signed-off-by: Edgar E. Iglesias
> > ---
> > hw/microblaze/petalogix_ml605_mmu.c | 17 -
> > 1 file cha
When using QEMU in some terminal environments, char back-ends for serial
devices can return EAGAIN for non trivial periods. This coupled with use
of qemu_chr_fe_write_all() is a leading cause of:
main-loop: WARNING: I/O thread spun for 1000 iterations
This series fixes this for cadence_uart by r
As per current QOM conventions.
Signed-off-by: Peter Crosthwaite
---
hw/char/cadence_uart.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
index f18db53..2f19a53 100644
--- a/hw/char/cadence_uart.c
+++ b/hw/char/cadence_uart.c
@@ -110,7 +11
This should be rechecked on bus write accesses as such accesses may
change the underlying state that generates the interrupt. Particular
relevant for when the guest touches the interrupt status or mask.
Signed-off-by: Peter Crosthwaite
---
hw/char/cadence_uart.c | 1 +
1 file changed, 1 inserti
Don't reset the uart as an init step. Register the reset function as a
proper reset fn instead.
Signed-off-by: Peter Crosthwaite
---
hw/char/cadence_uart.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
index a43f92c..2
Rename this field to match the many other uses of "rx". Xilinx
docmentation (UG585) also refers to this as "RxFIFO".
Signed-off-by: Peter Crosthwaite
---
hw/char/cadence_uart.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_u
The status register bits are always pure functions of other device
state. Move the generation of these bits to the update_status()
function to simplify. Makes developing much easier as theres now no need
to recheck status bits on all the changes to rx/tx fifo state.
Signed-off-by: Peter Crosthwait
Some (interrupt) status register bits relating to the TxFIFO path were
not defined. Define them. This prepares support for proper Tx data path
flow control.
Signed-off-by: Peter Crosthwaite
---
hw/char/cadence_uart.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/char/cadence_uart.c
This tx timer implementation is flawed. Despite the controller
attempting to time the guest visable assertion of the TX-empty status
bit (and corresponding interrupt) the controller is still transmitting
characters instantaneously. There is also no sense of multiple character
delay.
The only side
The can_receive logic was only taking into account the RxFIFO
occupancy. RxFIFO population is only used for the echo and normal modes
however. Improve the logic to correctly return the true number of
receivable characters based on the current mode:
Normal mode: RxFIFO vacancy.
Remote loopback: TxF
uart_rx_reset() called immediately above already does this. Remove.
Signed-off-by: Peter Crosthwaite
---
hw/char/cadence_uart.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
index cffb4c3..3be110c 100644
--- a/hw/char/cadence_uart.c
+++ b/h
Populate the TxFIFO with the Tx data before sending. Prepares
support for proper Tx flow control implementation.
Signed-off-by: Peter Crosthwaite
---
hw/char/cadence_uart.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/hw/char/cadence_uart.c b/hw/char/cad
If the UART back-end blocks, buffer in the Tx FIFO to try again later.
This stops the IO-thread busy waiting on char back-ends (which causes
all sorts of performance problems).
Signed-off-by: Peter Crosthwaite
---
hw/char/cadence_uart.c | 31 +--
1 file changed, 29 i
On Mon, Dec 16, 2013 at 04:21:28PM +0100, Antonios Motakis wrote:
>On Mon, Dec 16, 2013 at 8:32 AM, Edgar E. Iglesias
> wrote:
>
> On Fri, Dec 13, 2013 at 12:14:31PM +0100, Antonios Motakis wrote:
> > This option complements -mem-path. It implies -mem-prealloc. If
> specifie
On Mon, Dec 16, 2013 at 05:21:23PM +0800, Fam Zheng wrote:
> On 2013年12月11日 15:33, Hu Tao wrote:
> >On Thu, Nov 28, 2013 at 11:03:04AM +0100, Peter Lieven wrote:
> >>On 28.11.2013 09:48, Hu Tao wrote:
> >>>On Wed, Nov 27, 2013 at 11:13:40AM +0100, Peter Lieven wrote:
> Am 27.11.2013 11:07, schr
On 2013年12月12日 01:32, Eric Blake wrote:
On 12/11/2013 01:49 AM, Stefan Hajnoczi wrote:
We are moving boldly on to QEMU 2.0 in the next release. Some patches
written at a time where we assumed 1.8 would be the next version number
managed to sneak in.
s/1.8/2.0/ in qapi-schema.json
Signed-off-b
On 11/12/13 3:37 PM, Stefan Weil wrote:
The buildbot shows these compiler warnings:
block/vvfat.c: In function 'create_short_and_long_name':
block/vvfat.c:620: warning: array size (8) smaller than bound length (11)
block/vvfat.c:620: warning: array size (8) smaller than bound length (11)
block/v
On 2013年12月16日 23:34, Peter Lieven wrote:
This patch adds native support for accessing images on NFS shares without
the requirement to actually mount the entire NFS share on the host.
NFS Images can simply be specified by an url of the form:
nfs:
For example:
qemu-img create -f qcow2 nfs://
I'm trying to debug an issue with qemu 1.7, when altmbr.bin
from syslinux is unable to boot from a logical partition when
qemu emulates sata drive, but works just fine with ide drive.
While debugging, I noticed that sata drive has some other
interesting glitches too.
qemu-system-x86_64 -enable-kv
On Tue, Dec 17, 2013 at 12:15:54AM +, Peter Maydell wrote:
> On 16 December 2013 23:39, Christoffer Dall
> wrote:
> > On Thu, Nov 28, 2013 at 01:33:17PM +, Peter Maydell wrote
> >> --- a/target-arm/cpu.h
> >> +++ b/target-arm/cpu.h
> >> @@ -113,8 +113,13 @@ typedef struct CPUARMState {
>
On Tue, Dec 17, 2013 at 12:21:27AM +, Peter Maydell wrote:
> On 16 December 2013 23:39, Christoffer Dall
> wrote:
> > On Thu, Nov 28, 2013 at 01:33:18PM +, Peter Maydell wrote:
> >> +ahcc->target = init.target;
> >> +ahcc->dtb_compatible = "arm,arm-v7";
> >
> > arm,arm-v8 ?
>
> O
On Tue, Dec 17, 2013 at 12:25:43AM +, Peter Maydell wrote:
> On 16 December 2013 23:40, Christoffer Dall
> wrote:
> > On Thu, Nov 28, 2013 at 01:33:21PM +, Peter Maydell wrote:
> >> From: "Mian M. Hamayun"
> >>
> >> This commit adds support for booting a single AArch64 CPU by setting
> >
On Tue, Dec 17, 2013 at 11:24:45AM +1000, Peter Crosthwaite wrote:
> On Tue, Dec 17, 2013 at 10:58 AM, Peter Maydell
> wrote:
> > On 17 December 2013 00:52, Peter Crosthwaite
> > wrote:
> >> On Fri, Dec 13, 2013 at 8:05 PM, Peter Maydell
> >> wrote:
> >>> On 13 December 2013 03:19, Peter Crosth
The latest kernel headers update bf63839ffa2d0eebb1eb1706022f46e93b6fec08
"linux-headers: Update from v3.13-rc3" turned __KVM_HAVE_GUEST_DEBUG on
and broke the upstream for PPC64 as this API is not supported by PPC64 yet.
This adds no-op stubs (copied from target-arm/kvm.c).
Signed-off-by: Alexey
On (Mon) 16 Dec 2013 [15:19:31], Anthony Liguori wrote:
> On Mon, Dec 16, 2013 at 8:36 AM, Amit Shah wrote:
> > On (Mon) 09 Dec 2013 [22:10:12], Amos Kong wrote:
> >> Bugzilla: https://bugs.launchpad.net/qemu/+bug/1253563
> >>
> >> We have a requests queue to cache the random data, but the second
On 12/04/2013 04:34 PM, Alexey Kardashevskiy wrote:
> On 11/16/2013 03:58 AM, Alexey Kardashevskiy wrote:
>> On 16.11.2013 0:15, Alexander Graf wrote:
>>>
>>>
>>> Am 15.11.2013 um 00:12 schrieb Alexey Kardashevskiy :
>>>
At the moment only a whole CPU core can be assigned to a KVM. Since
On Tue, Dec 17, 2013 at 11:22:14AM +0530, Amit Shah wrote:
> On (Mon) 16 Dec 2013 [15:19:31], Anthony Liguori wrote:
> > On Mon, Dec 16, 2013 at 8:36 AM, Amit Shah wrote:
> > > On (Mon) 09 Dec 2013 [22:10:12], Amos Kong wrote:
> > >> Bugzilla: https://bugs.launchpad.net/qemu/+bug/1253563
> > >>
>
[Cc: Anthony, Mike for QAPI schema expertise]
Luiz Capitulino writes:
> On Tue, 10 Dec 2013 19:15:05 +0100
> Paolo Bonzini wrote:
>
>> -BEGIN PGP SIGNED MESSAGE-
>> Hash: SHA1
>>
>> Il 10/12/2013 19:00, Eric Blake ha scritto:
>> >>> + 'data': {'qom-type': 'str', 'id': 'str', '*props':
Amos Kong writes:
> Bugzilla: https://bugs.launchpad.net/qemu/+bug/1253563
>
> We have a requests queue to cache the random data, but the second
> will come in when the first request is returned, so we always
> only have one items in the queue. It effects the performance.
>
> This patch changes t
Hi Fam,
On 17.12.2013 05:07, Fam Zheng wrote:
On 2013年12月16日 23:34, Peter Lieven wrote:
This patch adds native support for accessing images on NFS shares without
the requirement to actually mount the entire NFS share on the host.
NFS Images can simply be specified by an url of the form:
nfs://
On Wed, 11 Dec 2013 18:07:58 +1100
Alexey Kardashevskiy wrote:
>
> Hm. Nack. This fails:
>
> ./qemu-system-ppc64 \
> -trace "events=qemu_trace_events" \
> -L "qemu-ppc64-bios/" \
> -nographic \
> -vga "none" \
> -device \
> virtio-blk-pci,id=virtioiblk0,drive=drive0,bootindex=20,ioeventfd=
Function iscsi_read10_task got additional parameters starting with version
libiscsi 1.5.0.
libiscsi 1.4.0 is still widely used (Debian wheezy, jessie and other Linux
distributions currently provide packages for QEMU which use it), so we
still need support for this older API.
Reviewed-by: Peter Li
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