On Sat, Dec 21, 2013 at 12:33 AM, Peter Maydell
wrote:
> On 20 December 2013 14:12, Fedorov Sergey wrote:
>> I've briefly looked at the v8 ARM ARM. As I can see there is no banked
>> system control registers in AArch64. Seems the concept is changed to provide
>> separate registers for each meanin
On 17 December 2013 15:12, Peter Maydell wrote:
> @@ -763,7 +807,7 @@ static void handle_sys(DisasContext *s, uint32_t insn,
> bool isread,
> }
>
> /* Check access permissions */
> -if (!cp_access_ok(env, ri, isread)) {
> +if (!cp_access_ok(s->current_pl, ri, isread)) {
>
If the input to float*_scalbn() is denormal then it represents
a number 0.[mantissabits] * 2^(1-exponentbias) (and the actual
exponent field is all zeroes). This means that when we convert
it to our unpacked encoding the unpacked exponent must be one
greater than for a normal number, which represen
On 16 December 2013 14:12, James Hogan wrote:
> In KVM mode the bootrom is loaded and executed from the last 1MB of
> DRAM.
>
> Based on "[PATCH 12/12] KVM/MIPS: General KVM support and support for
> SMP Guests" by Sanjay Lal .
>
> Signed-off-by: James Hogan
> Cc: Aurelien Jarno
> ---
> Changes
On 16 December 2013 14:12, James Hogan wrote:
> From: Sanjay Lal
>
> COP0 emulation is in-kernel for KVM, so inject IRQ2 (I/O) interrupts via
> ioctls.
>
> Signed-off-by: Sanjay Lal
> Signed-off-by: James Hogan
> Cc: Aurelien Jarno
> ---
> Changes in v2:
> - Expand commit message
> - Remove
On 16 December 2013 14:12, James Hogan wrote:
> From: Sanjay Lal
>
> MIPS/Linux is unusual in having 128 signals rather than just 64 like
> most other architectures. This means its sigmask is 16 bytes instead of
> 8, so correct kvm_set_signal_mask to pass the correct sigmask->len to
> KVM_SET_SIG
On 16 December 2013 14:12, James Hogan wrote:
> From: Sanjay Lal
>
> Enable KVM support for MIPS in the build system.
>
> Signed-off-by: Sanjay Lal
> Signed-off-by: James Hogan
> Cc: Aurelien Jarno
> ---
> Changes in v2:
> - Expand commit message
> - Remove GIC code
> - Create asm-mips syml
On 21 December 2013 16:59, Aurelien Jarno wrote:
> Signed-off-by: Aurelien Jarno
> ---
> target-sh4/translate.c | 31 ++-
> 1 file changed, 14 insertions(+), 17 deletions(-)
>
> diff --git a/target-sh4/translate.c b/target-sh4/translate.c
> index 26b45c1..23d51c6 10
Signed-off-by: Aurelien Jarno
---
target-sh4/translate.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index d816936..17b4abe 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -639,17 +639,15
Signed-off-by: Aurelien Jarno
---
target-sh4/translate.c | 31 ++-
1 file changed, 14 insertions(+), 17 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 26b45c1..23d51c6 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
Use the bit number for SR constants instead of using a bit mask. This
make possible to also use the constants for shifts.
Signed-off-by: Aurelien Jarno
---
target-sh4/cpu.c |3 +-
target-sh4/cpu.h | 30 +--
target-sh4/gdbstub.c |4 +--
target-sh4/helper.c
This patchset improves the SH4 emulation by using the lately added
TCG instructions, namely add2, sub2 and movcond. For that the T, Q and
M bits are split out from the SR register.
The last two patches are doing cleanup in the code.
Aurelien Jarno (8):
target-sh4: use bit number for SR constant
Signed-off-by: Aurelien Jarno
---
target-sh4/translate.c |1 -
1 file changed, 1 deletion(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 23d51c6..68767c6 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -18,7 +18,6 @@
*/
#define DEBUG_DISAS
-//#
Signed-off-by: Aurelien Jarno
---
target-sh4/translate.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 3af9ccd..3a3b2b6 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -796,12 +796,12 @@
Signed-off-by: Aurelien Jarno
---
target-sh4/translate.c | 15 ++-
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 17b4abe..3af9ccd 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -882,18 +882,15
Splitting Q and M out of SR, it's possible to optimize div1 by using
TCG code instead of an helper.
Signed-off-by: Aurelien Jarno
---
target-sh4/cpu.h | 13 --
target-sh4/helper.h|1 -
target-sh4/op_helper.c | 118
target-sh4/
In preparation for more efficient setting of this field.
Signed-off-by: Aurelien Jarno
---
target-sh4/cpu.h | 14 +++-
target-sh4/gdbstub.c |4 +-
target-sh4/helper.c|2 +-
target-sh4/op_helper.c | 32 ++--
target-sh4/translate.c | 205 ---
On Fri, Dec 20, 2013 at 12:02:24AM +0100, Alexander Graf wrote:
>
> On 19.12.2013, at 20:57, Anthony Liguori wrote:
>
> > Alexander Graf writes:
> >
> >> Hi Blue / Aurelien / Anthony,
> >>
> >> This is my current patch queue for s390. Please pull.
> >>
> >> Alex
> >>
> >>
> >> The followi
This patchset enable the usage of the movbe instruction, available on
Intel Atom and Intel Haswell CPU, in qemu_ldst routines, avoiding bswap
instructions before or after the store or loads. The availability of
this instruction is done at runtime using the cpuid instruction.
The last patch of the
TCG_TARGET_HAS_movcond_i32 is always defined to 1 in tcg-target.h, so
remove the corresponding #ifdef #endif sequence, left from a previous
refactoring.
Signed-off-by: Aurelien Jarno
---
tcg/i386/tcg-target.c |2 --
1 file changed, 2 deletions(-)
diff --git a/tcg/i386/tcg-target.c b/tcg/i38
The movbe instruction has been added on some Intel Atom CPUs and on
recent Intel Haswell CPUs. It allows to load/store a value and at the
same time bswap it.
This patch detects the avaibility of this instruction and when available
use it in the qemu load/store routines in replacement of load/store
P_REXW is defined has a constant at the beginning of i386/tcg-target.c,
but the corresponding bit is later used in a harcoded way, which defeat
the purpose of a constant.
Fix that by using a conditional expression operator instead of a shift.
On x86 this actually makes the code slightly smaller as
Add support for three-byte opcodes, starting with the 0x0f 0x38 prefix.
Use P_EXT2 as the new constant, and shift all other constants so that
P_EXT and P_EXT2 have neighbouring values.
Signed-off-by: Aurelien Jarno
---
tcg/i386/tcg-target.c | 22 --
1 file changed, 16 inser
Signed-off-by: Aurelien Jarno
---
disas/i386.c |8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/disas/i386.c b/disas/i386.c
index 47f1f2e..044e02c 100644
--- a/disas/i386.c
+++ b/disas/i386.c
@@ -2632,17 +2632,17 @@ static const struct dis386 prefix_user_table[][4] =
On Mon, Dec 16, 2013 at 02:12:43PM +, James Hogan wrote:
> From: Sanjay Lal
>
> COP0 emulation is in-kernel for KVM, so inject IRQ2 (I/O) interrupts via
> ioctls.
>
> Signed-off-by: Sanjay Lal
> Signed-off-by: James Hogan
> Cc: Aurelien Jarno
> ---
> Changes in v2:
> - Expand commit mess
On Mon, Dec 16, 2013 at 02:12:45PM +, James Hogan wrote:
> From: Sanjay Lal
>
> Enable KVM support for MIPS in the build system.
>
> Signed-off-by: Sanjay Lal
> Signed-off-by: James Hogan
> Cc: Aurelien Jarno
> ---
> Changes in v2:
> - Expand commit message
> - Remove GIC code
> - Crea
On Mon, Dec 16, 2013 at 02:12:44PM +, James Hogan wrote:
> In KVM mode the bootrom is loaded and executed from the last 1MB of
> DRAM.
>
> Based on "[PATCH 12/12] KVM/MIPS: General KVM support and support for
> SMP Guests" by Sanjay Lal .
>
> Signed-off-by: James Hogan
> Cc: Aurelien Jarno
On Mon, Dec 16, 2013 at 02:12:36PM +, James Hogan wrote:
> From: Sanjay Lal
>
> Compare/Count timer interrupts are handled in-kernel for KVM, so don't
> bother starting it in QEMU.
>
> Signed-off-by: Sanjay Lal
> Signed-off-by: James Hogan
> Cc: Aurelien Jarno
> ---
> Changes in v2:
> -
On Mon, Dec 16, 2013 at 02:12:42PM +, James Hogan wrote:
> From: Sanjay Lal
>
> Implement the main KVM arch API for MIPS.
>
> Signed-off-by: Sanjay Lal
> Signed-off-by: James Hogan
> Cc: Aurelien Jarno
> Cc: Gleb Natapov
> Cc: Paolo Bonzini
> ---
> Changes in v2:
> - Expand commit mess
On Mon, Dec 16, 2013 at 02:12:39PM +, James Hogan wrote:
> MIPS KVM trap & emulate mode (which is currently the only supported
> mode) has to add an extra kseg0/kseg1 at 0x4000 and an extra
> kseg2/kseg3 at 0x6000. Take this into account in
> get_physical_address() so that debug memory
On Mon, Dec 16, 2013 at 02:12:38PM +, James Hogan wrote:
> Add preprocessor definitions for 32bit segment bases for use in
> get_physical_address(). These will also be taken advantage of in the
> next patch which adds KVM awareness.
>
> Signed-off-by: James Hogan
> Cc: Aurelien Jarno
> ---
>
On Mon, Dec 16, 2013 at 02:12:40PM +, James Hogan wrote:
> From: Sanjay Lal
>
> MIPS/Linux is unusual in having 128 signals rather than just 64 like
> most other architectures. This means its sigmask is 16 bytes instead of
> 8, so correct kvm_set_signal_mask to pass the correct sigmask->len t
On Mon, Dec 16, 2013 at 02:12:37PM +, James Hogan wrote:
> From: Sanjay Lal
>
> Add APIs for converting between KVM guest KSEG0 addresses and guest
> physical addresses. These will be used for translating addresses when
> loading a kernel ELF in KVM mode.
>
> In KVM trap and emulate mode bot
On Mon, Dec 16, 2013 at 02:12:41PM +, James Hogan wrote:
> From: Sanjay Lal
>
> With larger set associative caches KVM can open the possibility of cache
> aliasing between the memory that QEMU allocates with mmap and the
> mapping into the guest address space. Therefore increase the target pa
Hi!
I am having a problem with virtio-net + vhost on POWER7 machine - it does
not survive reboot of the guest.
Steps to reproduce:
1. boot the guest
2. configure eth0 and do ping - everything works
3. reboot the guest (i.e. type "reboot")
4. when it is booted, eth0 can be configured but will not
On Sat, 21 Dec 2013 11:48:29 +0100
Markus Armbruster wrote:
> Igor Mammedov writes:
>
> > ---
> > tests/Makefile |3 +
> > tests/check-qom-interface.c | 102
> > +++
> > 2 files changed, 105 insertions(+), 0 deletions(-)
> > create mo
Il 21/12/2013 00:00, Richard Henderson ha scritto:
> +if (real_bswap && have_movbe) {
> +tcg_out_modrm_offset(s, OPC_MOVBE_GyMy + P_DATA16 + seg,
> + datalo, base, ofs);
> +tcg_out_ext16u(s, datalo, datalo);
Do partial register stalls
On 10/12/13 21:08, Mark Cave-Ayland wrote:
There's a fairly nasty regression in OpenBIOS for 1.7 which breaks
booting for SPARC32 disk images, along with a stack underflow which
affects all architectures during boot.
Please can you update the OpenBIOS git-svn mirror on git.qemu.org, and
let me
Public bug reported:
Hello.
I have a USB webcam I'm using under QEMU (version 1.6.1). The guest is
Windows 7 (32-bit) while the host is Gentoo Linux (64-bit). I have been
using it for several weeks without any problem, but now it doesn't work
any more. I have been able to pinpoint the cause: it i
Please also see https://bugs.gentoo.org/show_bug.cgi?id=494946
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https://bugs.launchpad.net/bugs/1263318
Title:
Cannot add a USB 2.0 device under QEMU when running eudev
Status in QEMU
Igor Mammedov writes:
> ---
> tests/Makefile |3 +
> tests/check-qom-interface.c | 102
> +++
> 2 files changed, 105 insertions(+), 0 deletions(-)
> create mode 100644 tests/check-qom-interface.c
>
> diff --git a/tests/Makefile b/tests/
Mike Qiu writes:
> Currently, if compile with Werror option, the error message shows
> below:
>
> GEN config-host.h
> GEN trace/generated-tracers.h
> CHK version_gen.h
> GEN trace/generated-tracers.c
> CCvl.o
> vl.c: In function ‘get_boot_devices_list’:
> vl.c:1257:21: e
Alexander Graf writes:
> When we have 2 separate qdev devices that both create a qbus of the
> same type without specifying a bus name or device name, we end up
> with two buses of the same name, such as ide.0 on the Mac machines:
>
> dev: macio-ide, id ""
> bus: ide.0
> type IDE
>
Convert the read, write, flush and discard implementations from aio-based
ones to coroutine based ones.
Signed-off-by: Bharata B Rao
---
block/gluster.c | 221 +++-
1 file changed, 74 insertions(+), 147 deletions(-)
diff --git a/block/gluster.
GlusterFS supports creation of zero-filled file on GlusterFS volume
by means of an API called glfs_zerofill(). Use this API from QEMU to
create an image that is filled with zeroes by using the preallocation
option of qemu-img.
qemu-img create gluster://server/volume/image -o preallocation=full 10G
Hi,
This series is about converting all the bdrv_aio* implementations in gluster
driver to coroutine based implementations. Read, write, flush and discard
routines are converted.
This also adds support for .bdrv_co_write_zeroes() in gluster and provides
a new preallocation option with qemu-img (-
Support .bdrv_co_write_zeroes() from gluster driver by using GlusterFS API
glfs_zerofill() that off-loads the writing of zeroes to GlusterFS server.
Signed-off-by: Bharata B Rao
---
block/gluster.c | 79 +++--
configure | 8 ++
2 fil
$:~/branches/ettercap (master) $ apt-cache show qemu
Package: qemu
Priority: optional
Section: otherosfs
Installed-Size: 556
Maintainer: Ubuntu Developers
Architecture: amd64
Version: 1.7.0+dfsg-2ubuntu4~saucy1
Suggests: qemu-user-static
Depends: qemu-system (>= 1.7.0+dfsg-2ubuntu4~saucy1), qemu-u
This my Debian system:
$ uname -a
Linux rolly 3.11-2-amd64 #1 SMP Debian 3.11.10-1 (2013-12-04) x86_64
GNU/Linux
I normally run my qemu chroot using schroot as follows:
schroot -c armhf
If I need to install packages I schroot as root:
schroot -c armhf -u root
In the chroot, I
I don't have a machine running Ubuntu. I onlu lodged a bug here because
this is the official bug tracker for Qemu.
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https://bugs.launchpad.net/bugs/1042388
Title:
qemu: Unsupported sys
Juan Quintela writes:
> Hi
>
> First of all, poll told to move the call earlier.
>
> 9:00 EST (15:00 CET or 6:00 Pacific)
ACK
> Are we having a call on the 24th? Do we have any topics? Are enough
> people not on vacation?
I'm not not on vacation, and I hope y'all aren't not on vacation, eith
but I just tried to install ghc, not to build it, can you try my ppa?
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https://bugs.launchpad.net/bugs/1042388
Title:
qemu: Unsupported syscall: 257 (timer_create)
Status in QEMU:
C
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