[Qemu-devel] [PATCH v2] docs/specs/qcow2.txt: fix incorrect bits of offsets in entries

2013-12-30 Thread Hu Tao
Fix incorrect bits of offsets in refcount table entry, l1 table entry and l2 table entry. See REFT_OFFSET_MASK, L1E_OFFSET_MASK and L2E_OFFSET_MASK. Fix a typo while at the file. Signed-off-by: Hu Tao hu...@cn.fujitsu.com --- v2: update comments as well. docs/specs/qcow2.txt | 14

[Qemu-devel] [PATCH 1/1] qtest:Fix the bug about disabling vnc causes make check hang

2013-12-30 Thread Kewei Yu
When we disabling vnc from ./configure, the qemu can't use the vnc option. So qtest can't use the vnc -none , otherwise make check will hang. Signed-off-by: Kewei Yu kewe...@gmail.com --- tests/fdc-test.c |4 tests/ide-test.c | 11 --- 2 files changed, 12 insertions(+), 3

Re: [Qemu-devel] [PATCH] sparc: Set HostID in NVRAM

2013-12-30 Thread Artyom Tarasenko
On Mon, Dec 30, 2013 at 12:51 AM, Olivier Danet oda...@caramail.com wrote: On SparcStations, the HostID field in the NVRAM is equal to the last three bytes of the MAC address (which is also stored in the NVRAM). This constant is used as an identification/serial number on Solaris.

Re: [Qemu-devel] correct TCG_CALL_* flags for helpers which directly access env fields?

2013-12-30 Thread Richard Henderson
On 12/28/2013 08:47 AM, Peter Maydell wrote: Assuming the fields it accesses aren't also being used for TCG memory globals, presumably NO_RWG_SE if the field is only read, and NO_RWG if it's written? Correct. r~

Re: [Qemu-devel] [V3 PATCH 02/14] target-ppc: Add ISA2.06 bpermd Instruction

2013-12-30 Thread Richard Henderson
On 12/27/2013 04:23 PM, Scott Wood wrote: On Tue, 2013-12-24 at 07:17 -0800, Richard Henderson wrote: On 12/18/2013 12:48 PM, Tom Musta wrote: +DEF_HELPER_3(bpermd, i64, env, i64, i64) Should be DEF_HELPER_FLAGS_2(bpermd, TCG_CALL_NO_RWG_SE, i64, i64, i64) +uint64_t

Re: [Qemu-devel] [PATCH 01/10] target-arm: A64: Add support for dumping AArch64 VFP register state

2013-12-30 Thread Richard Henderson
On 12/28/2013 01:49 PM, Peter Maydell wrote: +uint64_t vlo = float64_val(env-vfp.regs[i * 2]); +uint64_t vhi = float64_val(env-vfp.regs[(i * 2) + 1]); +cpu_fprintf(f, q%02d.0=%016 PRIx64 :%016 PRIx64 , +i, vlo, vhi); Why print them

Re: [Qemu-devel] [PATCH 02/10] target-arm: A64: Fix vector register access on bigendian hosts

2013-12-30 Thread Richard Henderson
On 12/28/2013 01:49 PM, Peter Maydell wrote: if (size 4) { switch (size) { case 0: -tcg_gen_ld8u_i64(tmp, cpu_env, freg_offs); +tcg_gen_ld8u_i64(tmp, cpu_env, fp_reg_offset(srcidx, MO_8)); break; case 1: -

Re: [Qemu-devel] [PATCH 03/10] target-arm: Use VFP_BINOP macro for min, max, minnum, maxnum

2013-12-30 Thread Richard Henderson
On 12/28/2013 01:49 PM, Peter Maydell wrote: Use the VFP_BINOP macro to provide helpers for min, max, minnum and maxnum, rather than hand-rolling them. (The float64 max version is not used by A32 but will be needed for A64.) Signed-off-by: Peter Maydell peter.mayd...@linaro.org ---

[Qemu-devel] [PATCH] smbus: do not immediately complete commands

2013-12-30 Thread Hervé Poussineau
PIIX4 errata says that immediate polling of the Host Status Register BUSY bit may indicate that the SMBus is NOT busy. This fixes some code which does the following steps: (a) set parameters (b) start command (c) check for smbus busy bit set (to know that command started) (d) check for smbus busy

Re: [Qemu-devel] [PATCH 04/10] target-arm: A64: Add Floating-point data-processing (2 source) insns

2013-12-30 Thread Richard Henderson
On 12/28/2013 01:49 PM, Peter Maydell wrote: From: Alexander Graf ag...@suse.de This patch adds emulation for the Floating-point data-processing (2 source) group of instructions. Signed-off-by: Alexander Graf ag...@suse.de [WN: Commit message tweak, merge single and double precision

Re: [Qemu-devel] [PATCH 05/10] target-arm: A64: Add Floating-point data-processing (3 source) insns

2013-12-30 Thread Richard Henderson
On 12/28/2013 01:49 PM, Peter Maydell wrote: +/* These are fused multiply-add, and must be done as one + * floating point operation with no rounding between the + * multiplication and addition steps. + * NB that doing the negations here as separate steps is + * correct :

Re: [Qemu-devel] [PATCH 05/10] target-arm: A64: Add Floating-point data-processing (3 source) insns

2013-12-30 Thread Richard Henderson
On 12/30/2013 07:15 AM, Richard Henderson wrote: On 12/28/2013 01:49 PM, Peter Maydell wrote: +/* These are fused multiply-add, and must be done as one + * floating point operation with no rounding between the + * multiplication and addition steps. + * NB that doing the

Re: [Qemu-devel] [PATCH 01/10] target-arm: A64: Add support for dumping AArch64 VFP register state

2013-12-30 Thread Peter Maydell
On 30 December 2013 14:58, Richard Henderson r...@twiddle.net wrote: On 12/28/2013 01:49 PM, Peter Maydell wrote: +uint64_t vlo = float64_val(env-vfp.regs[i * 2]); +uint64_t vhi = float64_val(env-vfp.regs[(i * 2) + 1]); +cpu_fprintf(f, q%02d.0=%016 PRIx64

Re: [Qemu-devel] [PATCH 06/10] target-arm: A64: Add fmov (scalar, immediate) instruction

2013-12-30 Thread Richard Henderson
On 12/28/2013 01:49 PM, Peter Maydell wrote: From: Alexander Graf ag...@suse.de This patch adds emulation for the fmov instruction working on scalars with an immediate payload. Signed-off-by: Alexander Graf ag...@suse.de [WN: Commit message tweak, rebase and use new infrastructure.]

Re: [Qemu-devel] [PATCH 07/10] target-arm: A64: Add support for floating point compare

2013-12-30 Thread Richard Henderson
On 12/28/2013 01:49 PM, Peter Maydell wrote: From: Claudio Fontana claudio.font...@linaro.org Add decoding support for C3.6.22 Floating-point compare. Signed-off-by: Claudio Fontana claudio.font...@linaro.org Signed-off-by: Peter Maydell peter.mayd...@linaro.org ---

Re: [Qemu-devel] [PATCH 08/10] target-arm: A64: Add support for floating point conditional compare

2013-12-30 Thread Richard Henderson
On 12/28/2013 01:49 PM, Peter Maydell wrote: From: Claudio Fontana claudio.font...@linaro.org This adds decoding support for C3.6.23 FP Conditional Compare. Signed-off-by: Claudio Fontana claudio.font...@linaro.org Signed-off-by: Peter Maydell peter.mayd...@linaro.org ---

Re: [Qemu-devel] [PATCH 02/10] target-arm: A64: Fix vector register access on bigendian hosts

2013-12-30 Thread Peter Maydell
On 30 December 2013 15:03, Richard Henderson r...@twiddle.net wrote: On 12/28/2013 01:49 PM, Peter Maydell wrote: if (size 4) { switch (size) { case 0: -tcg_gen_ld8u_i64(tmp, cpu_env, freg_offs); +tcg_gen_ld8u_i64(tmp, cpu_env,

Re: [Qemu-devel] [PATCH 09/10] target-arm: A64: Add support for floating point cond select

2013-12-30 Thread Richard Henderson
On 12/28/2013 01:49 PM, Peter Maydell wrote: From: Claudio Fontana claudio.font...@linaro.org This adds decoding support for C3.6.24 FP conditional select. Signed-off-by: Claudio Fontana claudio.font...@linaro.org Signed-off-by: Peter Maydell peter.mayd...@linaro.org ---

Re: [Qemu-devel] [PATCH 10/10] target-arm: Give the FPSCR rounding modes names

2013-12-30 Thread Richard Henderson
On 12/28/2013 01:49 PM, Peter Maydell wrote: From: Alexander Graf ag...@suse.de When setting rounding modes we currently just hardcode the numeric values for rounding modes in a big switch statement. With AArch64 support coming, we will need to refer to these rounding modes at different

Re: [Qemu-devel] [PATCH 02/10] target-arm: A64: Fix vector register access on bigendian hosts

2013-12-30 Thread Richard Henderson
On 12/30/2013 07:28 AM, Peter Maydell wrote: Yeah, we could do that. Will the optimiser optimise away the unnecessary extra load of the unused high 32 bits for the 32 bit or smaller case on a 32 bit host CPU? It should. We do transform qemu_st_i64 to qemu_st_i32 as appropriate for 32-bit

Re: [Qemu-devel] [Qemu-ppc] [V3 PATCH 02/14] target-ppc: Add ISA2.06 bpermd Instruction

2013-12-30 Thread Alexander Graf
Am 30.12.2013 um 15:48 schrieb Richard Henderson r...@twiddle.net: On 12/27/2013 04:23 PM, Scott Wood wrote: On Tue, 2013-12-24 at 07:17 -0800, Richard Henderson wrote: On 12/18/2013 12:48 PM, Tom Musta wrote: +DEF_HELPER_3(bpermd, i64, env, i64, i64) Should be

Re: [Qemu-devel] [Qemu-ppc] [V3 PATCH 02/14] target-ppc: Add ISA2.06 bpermd Instruction

2013-12-30 Thread Richard Henderson
On 12/30/2013 07:43 AM, Alexander Graf wrote: Yes you can, but we only expose 64bit capable cpus with TARGET_PPC64 defined. You couldn't select them with the 32bit target. Ah, well. That answers my question then, really. r~

[Qemu-devel] [PATCH v2 10/10] target-arm: Give the FPSCR rounding modes names

2013-12-30 Thread Peter Maydell
From: Alexander Graf ag...@suse.de When setting rounding modes we currently just hardcode the numeric values for rounding modes in a big switch statement. With AArch64 support coming, we will need to refer to these rounding modes at different places throughout the code though, so let's better

[Qemu-devel] [PATCH v2 00/10] A64 decoder patchset 5: most floating point

2013-12-30 Thread Peter Maydell
FP support patchset. Changes v1-v2: patch 1: correct format string, argument order issues patch 2: simplify do_fp_st by always loading 64 bits from the vfp regs entry patches 3-10 unchanged; all have been reviewed. This patchset sits on top of the previous one (now almost entirely

[Qemu-devel] [PATCH v2 03/10] target-arm: Use VFP_BINOP macro for min, max, minnum, maxnum

2013-12-30 Thread Peter Maydell
Use the VFP_BINOP macro to provide helpers for min, max, minnum and maxnum, rather than hand-rolling them. (The float64 max version is not used by A32 but will be needed for A64.) Signed-off-by: Peter Maydell peter.mayd...@linaro.org Reviewed-by: Richard Henderson r...@twiddle.net ---

[Qemu-devel] [PATCH v2 06/10] target-arm: A64: Add fmov (scalar, immediate) instruction

2013-12-30 Thread Peter Maydell
From: Alexander Graf ag...@suse.de This patch adds emulation for the fmov instruction working on scalars with an immediate payload. Signed-off-by: Alexander Graf ag...@suse.de [WN: Commit message tweak, rebase and use new infrastructure.] Signed-off-by: Will Newton will.new...@linaro.org

[Qemu-devel] [PATCH v2 08/10] target-arm: A64: Add support for floating point conditional compare

2013-12-30 Thread Peter Maydell
From: Claudio Fontana claudio.font...@linaro.org This adds decoding support for C3.6.23 FP Conditional Compare. Signed-off-by: Claudio Fontana claudio.font...@linaro.org Signed-off-by: Peter Maydell peter.mayd...@linaro.org Reviewed-by: Richard Henderson r...@twiddle.net ---

[Qemu-devel] [PATCH v2 05/10] target-arm: A64: Add Floating-point data-processing (3 source) insns

2013-12-30 Thread Peter Maydell
From: Alexander Graf ag...@suse.de This patch adds emulation for the Floating-point data-processing (3 source) group of instructions. Signed-off-by: Alexander Graf ag...@suse.de [WN: Commit message tweak, merged single and double precision patches. Implement using muladd as suggested by Richard

[Qemu-devel] [PATCH v2 01/10] target-arm: A64: Add support for dumping AArch64 VFP register state

2013-12-30 Thread Peter Maydell
From: Alexander Graf ag...@suse.de When dumping the current CPU state, we can also get a request to dump the FPU state along with the CPU's integer state. Add support to dump the VFP state when that flag is set, so that we can properly debug code that modifies floating point registers.

[Qemu-devel] [PATCH v2 04/10] target-arm: A64: Add Floating-point data-processing (2 source) insns

2013-12-30 Thread Peter Maydell
From: Alexander Graf ag...@suse.de This patch adds emulation for the Floating-point data-processing (2 source) group of instructions. Signed-off-by: Alexander Graf ag...@suse.de [WN: Commit message tweak, merge single and double precision patches. Rebase and update to new infrastructure.

[Qemu-devel] [PATCH v2 07/10] target-arm: A64: Add support for floating point compare

2013-12-30 Thread Peter Maydell
From: Claudio Fontana claudio.font...@linaro.org Add decoding support for C3.6.22 Floating-point compare. Signed-off-by: Claudio Fontana claudio.font...@linaro.org Signed-off-by: Peter Maydell peter.mayd...@linaro.org Reviewed-by: Richard Henderson r...@twiddle.net --- target-arm/helper-a64.c

[Qemu-devel] [PATCH v2 09/10] target-arm: A64: Add support for floating point cond select

2013-12-30 Thread Peter Maydell
From: Claudio Fontana claudio.font...@linaro.org This adds decoding support for C3.6.24 FP conditional select. Signed-off-by: Claudio Fontana claudio.font...@linaro.org Signed-off-by: Peter Maydell peter.mayd...@linaro.org Reviewed-by: Richard Henderson r...@twiddle.net ---

[Qemu-devel] [PATCH v2 02/10] target-arm: A64: Fix vector register access on bigendian hosts

2013-12-30 Thread Peter Maydell
The A64 128 bit vector registers are stored as a pair of uint64_t values in the register array. This means that if we're directly loading or storing a value of size less than 64 bits we must adjust the offset appropriately to account for whether the host is bigendian or not. Provide utility

Re: [Qemu-devel] [PATCH v2 01/10] target-arm: A64: Add support for dumping AArch64 VFP register state

2013-12-30 Thread Richard Henderson
On 12/30/2013 08:34 AM, Peter Maydell wrote: From: Alexander Graf ag...@suse.de When dumping the current CPU state, we can also get a request to dump the FPU state along with the CPU's integer state. Add support to dump the VFP state when that flag is set, so that we can properly debug

Re: [Qemu-devel] [PATCH v2 02/10] target-arm: A64: Fix vector register access on bigendian hosts

2013-12-30 Thread Richard Henderson
On 12/30/2013 08:34 AM, Peter Maydell wrote: The A64 128 bit vector registers are stored as a pair of uint64_t values in the register array. This means that if we're directly loading or storing a value of size less than 64 bits we must adjust the offset appropriately to account for whether

Re: [Qemu-devel] [PATCH] hw/arm/boot: Don't set up ATAGS for autogenerated dtb booting

2013-12-30 Thread Peter Crosthwaite
On Mon, Dec 30, 2013 at 12:20 AM, Peter Maydell peter.mayd...@linaro.org wrote: The code which decides whether to set up the ATAGS data structure on reset was using the wrong conditional, which meant we were creating an ATAGS structure when doing a device-tree boot if the dtb was autogenerated

[Qemu-devel] TRIM/DISCARD/UNMAP support on qemu-nbd

2013-12-30 Thread Teng-Feng Yang
Hi folks, I have been studying QCOW2 file format for a couple of days, and I am a little bit confused about whether QCOW2 supports UNMAP or not. As I surf through internet, some mailing list discussion had mentioned that qemu-nbd and nbd module both support UNMAP command. So I follow the steps

Re: [Qemu-devel] [PATCH 1/1] qtest:Fix the bug about disabling vnc causes make check hang

2013-12-30 Thread Andreas Färber
Hi, Am 30.12.2013 09:46, schrieb Kewei Yu: When we disabling vnc from ./configure, the qemu can't use the vnc option. So qtest can't use the vnc -none , otherwise make check will hang. Signed-off-by: Kewei Yu kewe...@gmail.com --- tests/fdc-test.c |4 tests/ide-test.c | 11

Re: [Qemu-devel] [Bug 1262081] Re: qemu-system-sparc in qemu 1.7.0 fails to boot with Sun ROM

2013-12-30 Thread Peter Bartoli
On Dec 28, 2013, at 2:00 AM, Artyom Tarasenko atar4q...@gmail.com wrote: Actually QEMU does set variables in NVRAM (hw/sparc/sun4m.c:151), and afaik uses the layout of open-sourced OBP. The problem is that earlier versions of OBP seemed to have a different layout, or maybe just a magic

[Qemu-devel] [PATCH v2 1/1] qtest: Fix the bug about disabling vnc causes make check hang

2013-12-30 Thread Kewei Yu
When we disabling vnc from ./configure, the qemu can't use the vnc option. So qtest can't use the vnc -none , otherwise make check will hang. Signed-off-by: Kewei Yu kewe...@gmail.com --- v2: Consolidate VNC macro's #ifdef'ery to one central point (tests/libqtest.c). tests/fdc-test.c |5