[Qemu-devel] [PATCH 25/26] tcg-aarch64: Merge tcg_out_movr with tcg_out_mov

In the one case we rely on zero-extension, use ORR directly. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 26 +- 1 file changed, 9 insertions(+), 17 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index 3bbd24c..0735ffe 10

[Qemu-devel] [PATCH 21/26] tcg-aarch64: Merge aarch64_ldst_get_data/type into tcg_out_op

Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 114 ++- 1 file changed, 33 insertions(+), 81 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index bf4b654..0746f2a 100644 --- a/tcg/aarch64/tcg-target.c +++

[Qemu-devel] [PATCH 24/26] tcg-aarch64: Prefer unsigned offsets before signed offsets for ldst

The assembler seems to prefer them, perhaps we should too. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index fde3df7..3bbd24c 100644 --- a/tcg/aarc

[Qemu-devel] [PATCH 22/26] tcg-aarch64: Replace aarch64_ldst_op_data with TCGMemOp

The definition of op_data included opcode bits, not just the size field of the various ldst instructions. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 111 +-- 1 file changed, 49 insertions(+), 62 deletions(-) diff --git a/tcg/aarch

[Qemu-devel] [PATCH 26/26] tcg-aarch64: Support stores of zero

Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 67 +--- 1 file changed, 24 insertions(+), 43 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index 0735ffe..f9d9703 100644 --- a/tcg/aarch64/tcg-target.c +++

[Qemu-devel] [PATCH 16/26] tcg-aarch64: Use tcg_out_call for qemu_ld/st

In some cases, a direct branch will be in range. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index 34eee6a..3b8aa7d 100644 --- a/tcg/aarch64/tcg-target.

[Qemu-devel] [PATCH 19/26] tcg-aarch64: Implement TCG_TARGET_HAS_new_ldst

Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 101 ++- tcg/aarch64/tcg-target.h | 2 +- 2 files changed, 39 insertions(+), 64 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index 3920f99..fa1a45d 10064

[Qemu-devel] [PATCH 18/26] tcg-aarch64: Use TCGMemOp in qemu_ld/st

Making the bswap conditional on the memop instead of a compile-time test instead. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 131 +++ 1 file changed, 63 insertions(+), 68 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aa

[Qemu-devel] [PATCH 23/26] tcg-aarch64: Replace aarch64_ldst_op_data with AArch64LdstType

The definition of op_type wasn't encoded for the proper shift for the field, making the implementations confusing. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 42 +- 1 file changed, 17 insertions(+), 25 deletions(-) diff --git a/tcg/aa

[Qemu-devel] [PATCH 15/26] tcg-aarch64: Avoid add with zero in tlb load

Some guest env are small enough to reach the tlb with only a 12-bit addition. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 28 +++- 1 file changed, 19 insertions(+), 9 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index

[Qemu-devel] [PATCH 14/26] tcg-aarch64: Implement tcg_register_jit

Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 84 +++- 1 file changed, 69 insertions(+), 15 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index 05857bf..aaa5f09 100644 --- a/tcg/aarch64/tcg-target.c +++

[Qemu-devel] [PATCH 11/26] tcg-aarch64: Reuse FP and LR in translated code

We don't need the FP within translated code, and the LR is otherwise unused. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 44 tcg/aarch64/tcg-target.h | 32 +--- 2 files changed, 33 insertions(+), 43 dele

[Qemu-devel] [PATCH 05/26] tcg-aarch64: Use ORRI in tcg_out_movi

The subset of logical immediates that we support is quite quick to test, and such constants are quite common to want to load. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 70 +++- 1 file changed, 39 insertions(+), 31 deletions(-) di

[Qemu-devel] [PATCH 20/26] tcg-aarch64: Introduce tcg_out_insn_3507

Cleaning up the implementation of REV and REV16 at the same time. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 22 ++ 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index fa1a45d..bf4b654 1

[Qemu-devel] [PATCH 13/26] tcg-aarch64: Rearrange prologue insn order

Loads LR earlier so that it's available for the return branch earlier. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 21 +++-- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index d391c10..0585

[Qemu-devel] [PATCH 09/26] tcg-aarch64: Create tcg_out_brcond

Rearrange code to put the compare and branch in the same place. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 34 ++ 1 file changed, 14 insertions(+), 20 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index 6d8b666

[Qemu-devel] [PATCH 17/26] tcg-aarch64: Use ADR to pass the return address to the ld/st helpers

Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 11 +-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index 3b8aa7d..26dc1ab 100644 --- a/tcg/aarch64/tcg-target.c +++ b/tcg/aarch64/tcg-target.c @@ -1061,6

[Qemu-devel] [PATCH 06/26] tcg-aarch64: Special case small constants in tcg_out_movi

Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index 0f23e43..417f51a 100644 --- a/tcg/aarch64/tcg-target.c +++ b/tcg/aarch64/tcg-target.c @@ -577,6 +577,16 @@ static

[Qemu-devel] [PATCH 10/26] tcg-aarch64: Use CBZ and CBNZ

A compare and branch against zero happens at the start of every single TB. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 26 -- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index 44d53

[Qemu-devel] [PATCH 12/26] tcg-aarch64: Introduce tcg_out_insn_3314

Combines 4 other inline functions and tidies the prologue. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 100 --- 1 file changed, 33 insertions(+), 67 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c inde

[Qemu-devel] [PATCH 02/26] tcg-aarch64: Use intptr_t apropriately

As opposed to tcg_target_long. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index 661a5af..6938248 100644 --- a/tcg/aarch64/tcg-target.c +++ b/tcg/a

[Qemu-devel] [PATCH 08/26] tcg-aarch64: Use symbolic names for branches

Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 74 1 file changed, 43 insertions(+), 31 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index 4944eb6..6d8b666 100644 --- a/tcg/aarch64/tcg-target.c +++

[Qemu-devel] [PATCH 04/26] tcg-aarch64: Use MOVN in tcg_out_movi

When profitable, initialize the register with MOVN instead of MOVZ, before setting the remaining lanes with MOVK. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 62 ++-- 1 file changed, 49 insertions(+), 13 deletions(-) diff --git a/t

[Qemu-devel] [PATCH 07/26] tcg-aarch64: Use adrp in tcg_out_movi

Loading an qemu pointer as an immediate happens often. E.g. - exit_tb $0x7fa8140013 + exit_tb $0x7f81ee0013 ... - : d2800260mov x0, #0x13 - : f2b50280movkx0, #0xa814, lsl #16 - : f2c00fe0movkx0, #0x7f, lsl #32 + : 90ff1000adrpx0, 0x7f81ee +

[Qemu-devel] [PATCH 03/26] tcg-aarch64: Use TCGType and TCGMemOp constants

Rather than raw constants that could mean anything. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 71 +--- 1 file changed, 37 insertions(+), 34 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index 69382

[Qemu-devel] [PATCH 00/26] tcg/aarch64 improvements, part 3

This is the last of my queued patches for aarch64. I didn't really see a good place to split this apart. r~ Richard Henderson (26): tcg-aarch64: Properly detect SIGSEGV writes tcg-aarch64: Use intptr_t apropriately tcg-aarch64: Use TCGType and TCGMemOp constants tcg-aarch64: Use MOVN i

[Qemu-devel] [PATCH 01/26] tcg-aarch64: Properly detect SIGSEGV writes

Since the kernel doesn't pass any info on the reason for the fault, disassemble the instruction to detect a store. Signed-off-by: Richard Henderson --- user-exec.c | 29 +++-- 1 file changed, 23 insertions(+), 6 deletions(-) diff --git a/user-exec.c b/user-exec.c index b

[Qemu-devel] [PATCH] mac99: Bring memory layout closer to real hardware

Try to better match the memory map of a PowerMac3,1 model by moving the pci-cfg mappings to where they are on a real machine. Also add the VGA card after the macio to let the latter be mapped from 0x8000 to match hardware. (On real hardware the graphics card is on a different bus but we don't s

Re: [Qemu-devel] [PATCH v2 00/25] A64: Neon patches, sixth set

On 03/14/2014 11:37 AM, Peter Maydell wrote: > Alex Bennée (11): > target-arm: A64: Fix bug in add_sub_ext handling of rn > target-arm: A64: Add last AdvSIMD Integer to FP ops > target-arm: A64: Add FSQRT to C3.6.17 (two misc) > target-arm: A64: Add remaining CLS/Z vector ops > target-arm

Re: [Qemu-devel] [PATCH v2 3/4] exynos4210: Set reset-cbar property of Cortex-A9 CPUs

On Tue, Mar 11, 2014 at 12:44 AM, Peter Maydell wrote: > Set the reset-cbar property of the Exynos4210 SoC's Cortex-A9 > CPUs, so that Linux doesn't misrecognize them as a broken > uniprocessor SoC. > > Signed-off-by: Peter Maydell Reviewed-by: Peter Crosthwaite > --- > hw/arm/exynos4210.c |

Re: [Qemu-devel] [PATCH v2 4/4] virt: Set reset-cbar on CPUs

On Tue, Mar 11, 2014 at 12:44 AM, Peter Maydell wrote: > Set the reset-cbar property on CPUs used by the virt board, > if they have it. This isn't necessary for correct functioning > under Linux (since the A9 isn't a valid CPU for the virt board), > but it is the correct behaviour. > > Signed-off-

[Qemu-devel] [PATCH] cpu: Move tcg_exit_req to the end of CPUState

Reverse an increase in the size of generated code. Cc: Andreas Färber Signed-off-by: Richard Henderson --- include/qom/cpu.h | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 06ee263..f99885a 100644 --- a/include/qom/cpu.h +++

[Qemu-devel] [PATCH for-2.1 1/2] i386/acpi-build: allow more than 255 elements in CPON

The build_ssdt() function builds a number of AML objects that are related to CPU hotplug, and whose IDs form a contiguous sequence of APIC IDs. (APIC IDs are in fact discontiguous, but this is the traditional interface: build a contiguous sequence from zero up that covers all possible APIC IDs.) Th

[Qemu-devel] [PATCH for-2.1 2/2] i386/acpi-build: support hotplug of VCPU with APIC ID 0xFF

Building on the previous patch, raise the maximal count of processor objects / NTFY branches / CPON elements from 255 to 256. This allows the VCPU with APIC ID 0xFF to be hotplugged. Signed-off-by: Laszlo Ersek --- hw/i386/acpi-build.c | 16 +++- 1 file changed, 11 insertions(+), 5 d

[Qemu-devel] [PATCH for-2.1 0/2] i386/acpi-build: support hotplug of VCPU with APIC ID 0xFF

The current SSDT generator doesn't support hotplug of the VCPU with APIC ID 0xFF; supply that functionality. The series depends on Eduardo's [Qemu-devel] [PATCH v4 0/7] pc: Ensure APIC ID limits before aborting or corrupting memory Regression tested with 4 VCPUs.

Re: [Qemu-devel] [PATCH v4 2/3] qapi: Add a primitive to include other files from a QAPI schema file

The Friday 14 Mar 2014 à 21:24:38 (+0100), Lluís Vilanova wrote : > Benoît Canet writes: > > > The Thursday 13 Mar 2014 à 19:05:12 (+0100), Lluís Vilanova wrote : > >> Eric Blake writes: > >> > >> > On 03/13/2014 09:33 AM, Benoît Canet wrote: > >> >>> We certainly can't do without comments. > >>

[Qemu-devel] [PULL 06/14] tcg-aarch64: Handle constant operands to and, or, xor

Handle a simplified set of logical immediates for the moment. The way gcc and binutils do it, with 52k worth of tables, and a binary search depth of log2(5334) = 13, seems slow for the most common cases. Signed-off-by: Richard Henderson Reviewed-by: Claudio Fontana Tested-by: Claudio Fontana -

[Qemu-devel] [PULL 07/14] tcg-aarch64: Support andc, orc, eqv, not, neg

Signed-off-by: Richard Henderson Reviewed-by: Claudio Fontana Tested-by: Claudio Fontana --- tcg/aarch64/tcg-target.c | 57 tcg/aarch64/tcg-target.h | 20 - 2 files changed, 67 insertions(+), 10 deletions(-) diff --git a/tcg/aarc

[Qemu-devel] [PATCH v2 02/25] target-arm: A64: Fix bug in add_sub_ext handling of rn

From: Alex Bennée rn == 31 always means SP (not XZR) whether an add_sub_ext instruction is setting the flags or not; only rd has behaviour dependent on whether we are setting flags. Reported-by: Laurent Desnogues Signed-off-by: Alex Bennée Signed-off-by: Peter Maydell --- target-arm/translat

[Qemu-devel] [PATCH v2 04/25] target-arm: A64: Add FSQRT to C3.6.17 (two misc)

From: Alex Bennée Implement FSQRT in the two-reg-misc category. GCC uses this instruction form. Signed-off-by: Alex Bennée Signed-off-by: Peter Maydell --- target-arm/translate-a64.c | 13 - 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/target-arm/translate-a64.c b

[Qemu-devel] [PULL 03/14] tcg-aarch64: Introduce tcg_out_insn_3401

This merges the implementation of tcg_out_addi and tcg_out_subi. Signed-off-by: Richard Henderson Reviewed-by: Claudio Fontana Tested-by: Claudio Fontana --- tcg/aarch64/tcg-target.c | 72 +--- 1 file changed, 26 insertions(+), 46 deletions(-) diff

[Qemu-devel] [PATCH v4 0/7] pc: Ensure APIC ID limits before aborting or corrupting memory

Changes v3 -> v4: * Commit message update on patch 5/7 * Small comment change (s/should/shall/) on patch 6/7 Changes v2 -> v3: * Don't use MAX_CPUMASK_BITS on acpi-build.c, use ACPI_CPU_HOTPLUG_ID_LIMIT; * Rename MAX_CPUMASK_BITS to MAX_CPUS, and document it; * Use MAX_CPUS when checking max_

Re: [Qemu-devel] [PATCH v4 2/3] qapi: Add a primitive to include other files from a QAPI schema file

Benoît Canet writes: > The Thursday 13 Mar 2014 à 19:05:12 (+0100), Lluís Vilanova wrote : >> Eric Blake writes: >> >> > On 03/13/2014 09:33 AM, Benoît Canet wrote: >> >>> We certainly can't do without comments. >> >>> >> >>> JSON is designed for easy data exchange, but we use it as programming

[Qemu-devel] [PULL 10/14] tcg-aarch64: Support deposit

Also tidy the implementation of ubfm, sbfm, extr in order to share code. Signed-off-by: Richard Henderson Reviewed-by: Claudio Fontana Tested-by: Claudio Fontana --- tcg/aarch64/tcg-target.c | 66 ++-- tcg/aarch64/tcg-target.h | 4 +-- 2 files chang

[Qemu-devel] semantics of qemu_peek_buffer ?

Hi Juan, What are the semantics of 'qemu_peek_buffer'? - is it supposed to guarantee (if there are no errors) that it will read 'size' bytes? (i.e. it should block) There are currently two users of it: * qemu_read_buffer which spins filling it's buffer up with repeated calls to qemu

[Qemu-devel] [PULL 14/14] tcg-aarch64: Introduce tcg_out_insn_3405

Cleaning up the implementation of tcg_out_movi at the same time. Signed-off-by: Richard Henderson Reviewed-by: Claudio Fontana Tested-by: Claudio Fontana --- tcg/aarch64/tcg-target.c | 48 +++- 1 file changed, 27 insertions(+), 21 deletions(-) diff

[Qemu-devel] [Bug 1290370] Re: FreeBSD 9.2 shell crashes when run with -smp 4 option

I tested on the commit f53f3d0a00b6df39ce8df -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1290370 Title: FreeBSD 9.2 shell crashes when run with -smp 4 option Status in QEMU: New Bug descripti

[Qemu-devel] [PULL 12/14] tcg-aarch64: Support muluh, mulsh

Signed-off-by: Richard Henderson Reviewed-by: Claudio Fontana Tested-by: Claudio Fontana --- tcg/aarch64/tcg-target.c | 12 tcg/aarch64/tcg-target.h | 4 ++-- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index

[Qemu-devel] [PULL 13/14] tcg-aarch64: Support div, rem

Clean up multiply at the same time. For remainder, generic code will produce mul+sub, whereas we can implement with msub. Signed-off-by: Richard Henderson Reviewed-by: Claudio Fontana Tested-by: Claudio Fontana --- tcg/aarch64/tcg-target.c | 50 +++-

[Qemu-devel] [PATCH] configure: Remove redundant message for -Werror

The compiler flag -Werror is printed (or not printed) as any other compiler flag which is part of QEMU_CFLAGS. Therefore an extra output line for -Werror is redundant and can be removed. Signed-off-by: Stefan Weil --- configure |1 - 1 file changed, 1 deletion(-) diff --git a/configure b/c

[Qemu-devel] [PULL 09/14] tcg-aarch64: Use tcg_out_insn for setcond

Signed-off-by: Richard Henderson Reviewed-by: Claudio Fontana Tested-by: Claudio Fontana --- tcg/aarch64/tcg-target.c | 12 +++- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index 7f41c75..c38e3c0 100644 --- a/tcg/aarc

[Qemu-devel] [PULL 11/14] tcg-aarch64: Support add2, sub2

Signed-off-by: Richard Henderson Reviewed-by: Claudio Fontana Tested-by: Claudio Fontana --- tcg/aarch64/tcg-target.c | 76 tcg/aarch64/tcg-target.h | 8 ++--- 2 files changed, 80 insertions(+), 4 deletions(-) diff --git a/tcg/aarch64/tcg-targe

[Qemu-devel] [PULL 08/14] tcg-aarch64: Support movcond

Signed-off-by: Richard Henderson Reviewed-by: Claudio Fontana Tested-by: Claudio Fontana --- tcg/aarch64/tcg-target.c | 34 ++ tcg/aarch64/tcg-target.h | 4 ++-- 2 files changed, 36 insertions(+), 2 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch

[Qemu-devel] [PULL 05/14] tcg-aarch64: Handle constant operands to add, sub, and compare

Signed-off-by: Richard Henderson Reviewed-by: Claudio Fontana Tested-by: Claudio Fontana --- tcg/aarch64/tcg-target.c | 100 --- 1 file changed, 78 insertions(+), 22 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index

[Qemu-devel] [PULL 01/14] tcg-aarch64: Introduce tcg_out_insn

Converting the add/sub (3.5.2) and logical shifted (3.5.10) instruction groups to the new scheme. Signed-off-by: Richard Henderson Reviewed-by: Claudio Fontana Tested-by: Claudio Fontana --- tcg/aarch64/tcg-target.c | 94 +--- 1 file changed, 58 inse

[Qemu-devel] [PULL 04/14] tcg-aarch64: Implement mov with tcg_out_insn

Avoid the magic numbers in the current implementation. Signed-off-by: Richard Henderson Reviewed-by: Claudio Fontana Tested-by: Claudio Fontana --- tcg/aarch64/tcg-target.c | 24 +--- 1 file changed, 9 insertions(+), 15 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/

[Qemu-devel] [PULL 02/14] tcg-aarch64: Convert shift insns to tcg_out_insn

Signed-off-by: Richard Henderson Reviewed-by: Claudio Fontana Tested-by: Claudio Fontana --- tcg/aarch64/tcg-target.c | 52 +++- 1 file changed, 21 insertions(+), 31 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index

[Qemu-devel] [PULL 00/14] tcg/aarch64 improvements, part 2

Recently reviewed. It'd be nice if this makes -rc1, since it significantly improves code generation for the host. But it's no big deal if it's too late. r~ The following changes since commit b19fc63cadb2815d5bcb1ec25b22849e455cbb31: Merge remote-tracking branch 'remotes/afaerber/tags/qom-d

[Qemu-devel] [PATCH] configure: Show trace output file conditionally

It is only used with the simple trace backend. Signed-off-by: Stefan Weil --- configure |2 ++ 1 file changed, 2 insertions(+) diff --git a/configure b/configure index 1efb438..6eebd2c 100755 --- a/configure +++ b/configure @@ -4092,7 +4092,9 @@ echo "libcap-ng support $cap_ng" echo "vhost

[Qemu-devel] [PATCH v2 14/25] target-arm: A64: Implement SRI

Implement SRI (shift right and insert). Signed-off-by: Peter Maydell --- target-arm/translate-a64.c | 57 +++--- 1 file changed, 49 insertions(+), 8 deletions(-) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 86e5d3e..b67cd1d 1

[Qemu-devel] [PATCH v2 12/25] target-arm: A64: List unsupported shift-imm opcodes

Add the remaining unsupported opcodes to the decode switches for the shift-imm and scalar shift-imm categories so we can see what is still to be implemented. Signed-off-by: Peter Maydell --- target-arm/translate-a64.c | 13 +++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --g

Re: [Qemu-devel] [PATCH v4 7/7] vl.c: Use MAX_CPUS macro instead of hardcoded constant

On 03/14/14 20:33, Eduardo Habkost wrote: > Signed-off-by: Eduardo Habkost > --- > vl.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/vl.c b/vl.c > index 64b38a5..62cc734 100644 > --- a/vl.c > +++ b/vl.c > @@ -1413,7 +1413,7 @@ static void smp_parse(QemuOpts *opts) >

Re: [Qemu-devel] [PATCH v3 4/7] acpi: Don't use MAX_CPUMASK_BITS for APIC ID bitmap

On 03/14/14 20:03, Laszlo Ersek wrote: > On 03/14/14 19:52, Eduardo Habkost wrote: >> MAX_CPUMASK_BITS is a limit for max_cpus and CPU indexes, not for APIC >> IDs. >> >> ACPI_CPU_HOTPLUG_ID_LIMIT is the right macro for the limit on APIC IDs >> on the ACPI and CPU hotplug code. >> >> There are no f

Re: [Qemu-devel] [Qemu-trivial] [PATCH for-2.0] scripts/make-release: Don't distribute .git directories

14.03.2014 22:30, Laszlo Ersek wrote: [] > but did you in fact mean > > pixman/*.git > > rather tan > > pixman/.git This has been fixed in a v2 patch, which I applied to -trivial. Thanks, /mjt

Re: [Qemu-devel] [PATCH v3 7/7] vl.c: Use MAX_CPUS macro instead of hardcoded constant

On 03/14/14 20:30, Eduardo Habkost wrote: > On Fri, Mar 14, 2014 at 08:11:50PM +0100, Laszlo Ersek wrote: >> On 03/14/14 19:52, Eduardo Habkost wrote: >>> Signed-off-by: Eduardo Habkost >>> --- >>> vl.c | 2 +- >>> 1 file changed, 1 insertion(+), 1 deletion(-) >>> >>> diff --git a/vl.c b/vl.c >>>

[Qemu-devel] [PATCH v4 6/7] vl.c: Rename MAX_CPUMASK_BITS to MAX_CPUS

Also, document what the macro is really useful for. Signed-off-by: Eduardo Habkost Reviewed-by: Laszlo Ersek --- Changes v3 -> v4: * s/should/shall/ at the MAX_CPUS comment --- include/sysemu/sysemu.h | 9 - vl.c| 10 +- 2 files changed, 13 insertions(+),

Re: [Qemu-devel] SMBIOS vs. NUMA (was: Build full type 19 tables)

On Fri, Mar 14, 2014 at 06:51:05PM +0100, Igor Mammedov wrote: > > 1. is it safe to assume that E820_RAM (start_addr, size) entries are > > non-overlapping and sorted by increasing start_addr ? > They might overlap, grep for e820_add_entry(). If you interested in > what kernel does with such table

[Qemu-devel] [PATCH v4 2/7] pc: Refuse CPU hotplug if the resulting APIC ID is too large

The ACPI CPU hotplug code requires APIC IDs to be smaller than ACPI_CPU_HOTPLUG_ID_LIMIT, so enforce the limit before trying to hotplug a new vCPU, returning an error instead of crashing. Signed-off-by: Eduardo Habkost Reviewed-by: Laszlo Ersek --- hw/i386/pc.c | 8 1 file changed, 8 i

[Qemu-devel] [PATCH v4 5/7] pc: Refuse max_cpus if it results in too large APIC ID

This changes the PC initialization code to reject max_cpus if it results in an APIC ID that's too large, instead of aborting or erroring out when it is already too late. Signed-off-by: Eduardo Habkost Reviewed-by: Laszlo Ersek --- Changes v3 -> v4: * Commit message update: removed outdated comm

[Qemu-devel] [PATCH v4 7/7] vl.c: Use MAX_CPUS macro instead of hardcoded constant

Signed-off-by: Eduardo Habkost --- vl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vl.c b/vl.c index 64b38a5..62cc734 100644 --- a/vl.c +++ b/vl.c @@ -1413,7 +1413,7 @@ static void smp_parse(QemuOpts *opts) max_cpus = smp_cpus; } -if (max_cpus > 255) {

[Qemu-devel] [PATCH v4 3/7] acpi: Assert sts array limit on AcpiCpuHotplug_add()

AcpiCpuHotplug_add() can't handle vCPU arch IDs larger than ACPI_CPU_HOTPLUG_ID_LIMIT. Instead of corrupting memory in case the vCPU ID is too large, use g_assert() to ensure we are not over the limit. Signed-off-by: Eduardo Habkost Reviewed-by: Laszlo Ersek --- hw/acpi/cpu_hotplug.c | 1 + 1 f

[Qemu-devel] [PATCH v4 4/7] acpi: Don't use MAX_CPUMASK_BITS for APIC ID bitmap

MAX_CPUMASK_BITS is a limit for max_cpus and CPU indexes, not for APIC IDs. ACPI_CPU_HOTPLUG_ID_LIMIT is the right macro for the limit on APIC IDs on the ACPI and CPU hotplug code. There are no functional changes introduced by this patch, as MAX_CPUMASK_BITS + 1 == 255 + 1 == 256 == ACPI_CPU_HOTP

[Qemu-devel] [PATCH v4 1/7] acpi: Add ACPI_CPU_HOTPLUG_ID_LIMIT macro

The new macro will be helpful to allow us to detect too large SMP limits before it is too late. Signed-off-by: Eduardo Habkost Reviewed-by: Laszlo Ersek --- include/hw/acpi/cpu_hotplug_defs.h | 8 1 file changed, 8 insertions(+) diff --git a/include/hw/acpi/cpu_hotplug_defs.h b/inclu

Re: [Qemu-devel] [PATCH v3 7/7] vl.c: Use MAX_CPUS macro instead of hardcoded constant

On Fri, Mar 14, 2014 at 08:11:50PM +0100, Laszlo Ersek wrote: > On 03/14/14 19:52, Eduardo Habkost wrote: > > Signed-off-by: Eduardo Habkost > > --- > > vl.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/vl.c b/vl.c > > index 64b38a5..62cc734 100644 > > --- a/vl.

[Qemu-devel] [PATCH v2 09/25] target-arm: A64: Implement FCVT[NMAPZ][SU] SIMD instructions

Implement the floating-point-to-integer conversion instructions FCVT[NMAPZ][SU] in the 2-reg-misc and scalar-2-reg-misc categories. Signed-off-by: Peter Maydell --- target-arm/translate-a64.c | 188 - 1 file changed, 169 insertions(+), 19 deletions(-)

Re: [Qemu-devel] [PATCH v3 7/7] vl.c: Use MAX_CPUS macro instead of hardcoded constant

On 03/14/14 19:52, Eduardo Habkost wrote: > Signed-off-by: Eduardo Habkost > --- > vl.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/vl.c b/vl.c > index 64b38a5..62cc734 100644 > --- a/vl.c > +++ b/vl.c > @@ -1413,7 +1413,7 @@ static void smp_parse(QemuOpts *opts) >

[Qemu-devel] [PATCH v2 20/25] target-arm: A64: Implement AdvSIMD reciprocal estimate insns URECPE, FRECPE

From: Alex Bennée Implement URECPE and FRECPE instructions in both scalar and vector forms. The actual reciprocal estimate function is shared with the A32/T32 Neon code. However in A64 we aren't using the Neon "standard FPSCR value" so extra checks are necessary to handle non-squashed denormal in

[Qemu-devel] [PATCH v2 24/25] target-arm: A64: Add [UF]RSQRTE (reciprocal root estimate)

From: Alex Bennée This adds support for [UF]RSQRTE instructions. It utilises the existing NEON helpers with some changes. The changes include an explicit passing of fpstatus (so the correct one is used between arm32 and aarch64), denormilzation, more correct error handling and also proper scaling

Re: [Qemu-devel] [PATCH v3 6/7] vl.c: Rename MAX_CPUMASK_BITS to MAX_CPUS

one important nit :) On 03/14/14 19:52, Eduardo Habkost wrote: > Also, document what the macro is really useful for. > > Signed-off-by: Eduardo Habkost > --- > include/sysemu/sysemu.h | 9 - > vl.c| 10 +- > 2 files changed, 13 insertions(+), 6 deletions(-)

Re: [Qemu-devel] [PATCH v3 5/7] pc: Refuse max_cpus if it results in too large APIC ID

On 03/14/14 19:52, Eduardo Habkost wrote: > This changes the PC initialization code to reject max_cpus if it results > in an APIC ID that's too large, instead of aborting or erroring out when > it is already too late. > > Currently there are two limits we need to check: the CPU hotplug APIC ID > l

Re: [Qemu-devel] [PATCH] block: Explicitly specify 'unsigned long long' for VHDX 64-bit constants

On 03/14/14 19:49, Laszlo Ersek wrote: > One good example is for 6.4.4.1 "Integer constants": > > QUIET CHANGE IN C99 > > Unsuffixed integer constants may have different types in C99 than > in C89. Such constants greater than LONG_MAX are of type unsigned > long

Re: [Qemu-devel] [PATCH v3 4/7] acpi: Don't use MAX_CPUMASK_BITS for APIC ID bitmap

On 03/14/14 19:52, Eduardo Habkost wrote: > MAX_CPUMASK_BITS is a limit for max_cpus and CPU indexes, not for APIC > IDs. > > ACPI_CPU_HOTPLUG_ID_LIMIT is the right macro for the limit on APIC IDs > on the ACPI and CPU hotplug code. > > There are no functional changes introduced by this patch, as

[Qemu-devel] [PATCH v2 11/25] target-arm: A64: Implement FCVTL

Implement FCVTL, the only instruction in the 2-reg-misc group which widens from size to 2*size elements. Signed-off-by: Peter Maydell --- target-arm/translate-a64.c | 47 ++ 1 file changed, 47 insertions(+) diff --git a/target-arm/translate-a64.c b/ta

[Qemu-devel] [PATCH v2 13/25] target-arm: A64: Add FRECPX (reciprocal exponent)

From: Alex Bennée These are fairly simple exponent only estimation functions using helpers. Signed-off-by: Alex Bennée Signed-off-by: Peter Maydell --- target-arm/helper-a64.c| 59 ++ target-arm/helper-a64.h| 2 ++ target-arm/translate-a64.c | 70 +

[Qemu-devel] [PATCH v2 25/25] scripts/qemu-binfmt-conf.sh: Add AArch64 registration

Add the binfmt-misc magic needed to register QEMU for handling AArch64 ELF binaries. Signed-off-by: Peter Maydell --- scripts/qemu-binfmt-conf.sh | 3 +++ 1 file changed, 3 insertions(+) diff --git a/scripts/qemu-binfmt-conf.sh b/scripts/qemu-binfmt-conf.sh index 0da2618..289b1a3 100644 --- a/s

[Qemu-devel] [PATCH v2 01/25] target-arm: A64: Implement PMULL instruction

Implement the PMULL instruction; this is the last unimplemented insn in the three-reg-diff group. Note that PMULL with size 3 is considered part of the AES part of the crypto extensions (see the ID_AA64ISAR0_EL1 register definition in the v8 ARM ARM), so it isn't necessary to burn an extra feature

[Qemu-devel] [PATCH v2 18/25] target-arm: A64: Implement FCVTZS, FCVTZU in the shift-imm categories

Implement FCVTZS and FCVTZU in the shift-imm and scalar-shift-imm categories; this completes the implementation of those two groups. Signed-off-by: Peter Maydell --- target-arm/translate-a64.c | 80 -- 1 file changed, 78 insertions(+), 2 deletions(-)

[Qemu-devel] [PATCH v2 22/25] target-arm: A64: Implement scalar saturating narrow ops

From: Alex Bennée This completes the set of integer narrowing saturating ops including: SQXTN, SQXTN2 SQXTUN, SQXTUN2 UQXTN, UQXTN2 Signed-off-by: Alex Bennée Signed-off-by: Peter Maydell --- target-arm/translate-a64.c | 35 --- 1 file changed, 2

[Qemu-devel] [PATCH v2 03/25] target-arm: A64: Add last AdvSIMD Integer to FP ops

From: Alex Bennée This adds the remaining [US]CVTF operations to the SIMD shift-immediate, scalar-shift-immediate, two-reg-misc and scalar-two-reg-misc groups of opcodes. Signed-off-by: Alex Bennée [PMM: added scalar 2-misc and scalar-shift-imm encodings] Signed-off-by: Peter Maydell --- targ

[Qemu-devel] [PATCH v2 16/25] exec-all.h: Increase MAX_OP_PER_INSTR for ARM A64 decoder

The ARM A64 decoder's worst case number of TCG ops per instruction is 266 (for insn 0x4c80, a post-indexed ST4 multiple-structures store). Raise the MAX_OP_PER_INSTR define accordingly. Signed-off-by: Peter Maydell --- include/exec/exec-all.h | 2 +- 1 file changed, 1 insertion(+), 1 deletio

[Qemu-devel] [PATCH v2 19/25] softfloat: export squash_input_denormal functions

From: Alex Bennée I need these available outside of softfloat for some of the reciprocal processing in aarch64 helper functions. Signed-off-by: Alex Bennée Signed-off-by: Peter Maydell --- fpu/softfloat.c | 4 ++-- include/fpu/softfloat.h | 7 +++ 2 files changed, 9 insertions(+),

[Qemu-devel] [PATCH v2 17/25] target-arm: A64: Handle saturating left shifts SQSHL, SQSHLU, UQSHL

Implement the saturating left shift instructions SQSHL, SQSHLU and UQSHL for the scalar-shift-imm and shift-imm categories. Signed-off-by: Peter Maydell --- target-arm/translate-a64.c | 132 + 1 file changed, 132 insertions(+) diff --git a/target-arm/

[Qemu-devel] [PATCH v2 06/25] target-arm: A64: Saturating and narrowing shift ops

From: Alex Bennée This implements the remaining [US][Q][R]SHR[U][N][2] opcodes, which are saturating and narrowing shift right operations. These are used in things like libav. Note signed shifts can have an "unsigned" saturating narrow operation which will floor negative values. Signed-off-by: A

[Qemu-devel] [PATCH v2 15/25] target-arm: A64: Implement FRINT*

Implement the FRINT* round-to-integral operations from the 2-reg-misc category. Signed-off-by: Peter Maydell --- target-arm/translate-a64.c | 45 ++--- 1 file changed, 42 insertions(+), 3 deletions(-) diff --git a/target-arm/translate-a64.c b/target-arm/t

[Qemu-devel] [PATCH v3 5/7] pc: Refuse max_cpus if it results in too large APIC ID

This changes the PC initialization code to reject max_cpus if it results in an APIC ID that's too large, instead of aborting or erroring out when it is already too late. Currently there are two limits we need to check: the CPU hotplug APIC ID limit (due to the AcpiCpuHotplug.sts array length), and

[Qemu-devel] [PATCH v2 05/25] target-arm: A64: Add remaining CLS/Z vector ops

From: Alex Bennée Implement the CLS, CLZ operations in the 2-reg-misc category. Signed-off-by: Alex Bennée Signed-off-by: Peter Maydell --- target-arm/helper-a64.c| 5 + target-arm/helper-a64.h| 1 + target-arm/translate-a64.c | 36 +++- 3 files c

[Qemu-devel] [PATCH v2 00/25] A64: Neon patches, sixth set

Hi. This is a second version of the A64 Neon patchset six which I sent out a little while back. Changes: * fixed the 'hunk in wrong patch' snafu * adjusted FCVTN to pass 'size - 1' to handle_2misc_narrow; this puts it in line with other callers and means the function always takes the size o

[Qemu-devel] [PATCH v2 08/25] target-arm: A64: Implement SHLL, SHLL2

Implement the SHLL and SHLL2 instructions from the 2-reg-misc category. Signed-off-by: Peter Maydell --- target-arm/translate-a64.c | 32 +++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 4

[Qemu-devel] [PATCH v3 6/7] vl.c: Rename MAX_CPUMASK_BITS to MAX_CPUS

Also, document what the macro is really useful for. Signed-off-by: Eduardo Habkost --- include/sysemu/sysemu.h | 9 - vl.c| 10 +- 2 files changed, 13 insertions(+), 6 deletions(-) diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h index b90df9a.

[Qemu-devel] [PATCH v3 2/7] pc: Refuse CPU hotplug if the resulting APIC ID is too large

The ACPI CPU hotplug code requires APIC IDs to be smaller than ACPI_CPU_HOTPLUG_ID_LIMIT, so enforce the limit before trying to hotplug a new vCPU, returning an error instead of crashing. Signed-off-by: Eduardo Habkost Reviewed-by: Laszlo Ersek --- hw/i386/pc.c | 8 1 file changed, 8 i

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