Il 01/07/2014 07:42, Alexey Kardashevskiy ha scritto:
This is wrong actually. The problem here that compiler knows how to
optimize constants. sin(0.0) is the one while log(0.0) is not (it is
supposed to throw error or something as it the result is infinity).
So the correct test here could be:
in
** Changed in: linux (Ubuntu)
Status: Incomplete => Confirmed
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Title:
guest hang due to missing clock interrupt
Status in QEMU:
New
St
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Title:
gue
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Title:
g
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AlsaDevices:
total 0
crw-rw 1 root audio 116, 1 июня 30 18:31 seq
crw-rw 1 root audio 116, 33 июня 30 18:31 timer
AplayDevices: Error: [Errno 2] No such file or directory
ApportVersion: 2.14.1-0ubuntu3.2
Architecture: amd64
ArecordDevices: Error: [Errno 2] No such file or directory
Au
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gue
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Tit
Public bug reported:
http://git.qemu.org/?p=qemu.git;a=blob;f=hw/pci-
host/bonito.c;h=56292adb03cd1a9873c2c9e5a0b2978fd0572214;hb=master#l301
The switch statement is error-prone, since two branches return the same
result.
Segfault reproducing steps:
1. make a Linux kernel(for example 3.16.0-rc2)
Il 01/07/2014 03:05, Ming Lei ha scritto:
> Busy waiting is not acceptable here (it can be unbounded if, for example, an
> NFS server is on the other side of a network partition). You have to add a
> bottom half to qemu_laio_state that calls ioq_submit, and schedule it after
> calling io_getevent
On Mon, Jun 30, 2014 at 08:34:46PM +0100, Stefano Stabellini wrote:
> On Fri, 27 Jun 2014, Chen, Tiejun wrote:
> > On 2014/6/25 17:58, Chen, Tiejun wrote:
> > > On 2014/6/25 17:44, Michael S. Tsirkin wrote:
> > > > On Wed, Jun 25, 2014 at 05:28:48PM +0800, Chen, Tiejun wrote:
> > > > > On 2014/6/25
On 07/01/2014 11:51 AM, Alexey Kardashevskiy wrote:
> The existing test whether "-lm" needs to be included or not is
> insufficient as it reports false negative on Fedora20/ppc64.
> As the result, qemu-nbd/qemu-io/qemu-img tools cannot compile.
>
> This replaces sin() with log() in the test.
>
>
On Mon, Jun 30, 2014 at 03:31:05PM -0400, Ross Philipson wrote:
> On 06/30/2014 03:22 PM, Stefano Stabellini wrote:
> >On Mon, 30 Jun 2014, Michael S. Tsirkin wrote:
> >>On Mon, Jun 30, 2014 at 03:24:58PM +0800, Chen, Tiejun wrote:
> >>>On 2014/6/30 14:48, Michael S. Tsirkin wrote:
> On Mon, Ju
> Am 01.07.2014 um 05:20 schrieb Nikunj A Dadhania :
>
> Alexander Graf writes:
>
>>> On 30.06.2014, at 17:49, Tyrel Datwyler
>>> wrote:
>>>
On 06/30/2014 01:35 AM, Nikunj A Dadhania wrote:
PAPR compliant guest calls this in absence of kdump. This finally
reaches the guest an
On Tue, Jul 01, 2014 at 05:34:45AM +0100, Al Viro wrote:
> VAX operations are serious mess, but I'm not sure if we have them actually
> used anywhere in Linux kernel or userland. Always possible, of course, but...
Grr... Truncated mail, sorry. Missing part:
_If_ we decide that we want CVTGQ w
On Mon, Jun 30, 2014 at 09:56:35PM +0100, Al Viro wrote:
> FWIW, it might be better to do what float64_to_int64_round_to_zero() is doing
> -
> i.e.
> if (shift >= 0) {
> if (shift < 64)
> ret = frac << shift;
> if (shift < 11 || a == LIT64(0x
It does a g_free() on the pointer, so don't pass a local &foo reference.
Reviewed-by: Peter Crosthwaite
Reviewed-by: Peter Maydell
Cc: qemu-sta...@nongnu.org
Signed-off-by: Andreas Färber
---
hw/sd/sdhci.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/sd/sdhci.c b/
> Am 30.06.2014 um 23:47 schrieb "Stalley, Sean" :
>
>
>
>> -Original Message-
>> From: Alexander Graf [mailto:ag...@suse.de]
>> Sent: Monday, June 30, 2014 1:22 PM
>> To: Stalley, Sean; Peter Crosthwaite
>> Cc: qemu-devel@nongnu.org
>> Subject: Re: [Qemu-devel] Adding memory region wi
Replace qemu_allocate_irqs(foo, bar, 1)[0]
with qemu_allocate_irq(foo, bar, 0).
This avoids leaking the dereferenced qemu_irq *.
Cc: Markus Armbruster
Reviewed-by: Peter Crosthwaite
Reviewed-by: Peter Maydell
Signed-off-by: Andreas Färber
[PC Changes:
* Applied change to instance in sh4/sh77
Alexander Graf writes:
> On 30.06.2014, at 17:49, Tyrel Datwyler
> wrote:
>
>> On 06/30/2014 01:35 AM, Nikunj A Dadhania wrote:
>>> PAPR compliant guest calls this in absence of kdump. This finally
>>> reaches the guest and can be handled according to the policies set by
>>> higher level tools(
From: Peter Crosthwaite
Allocate each IRQ individually on array allocations. This prepares for
QOMification of IRQs, where pointers to individual IRQs may be taken
and handed around for usage as QOM Links. The g_renew() scheme used here
is too fragile and would break all existing links should an
As a prequel to any big Pin refactoring plans, do an in-place conversion
of qemu_irq to an Object, so that we can reference it in link<> properties.
Signed-off-by: Andreas Färber
[ PC Changes:
* Removed array-alloctor ref counting logic (limit changes just to
* single IRQ allocator)
* Removed
From: Peter Crosthwaite
Certain parts of the QOM framework test this pointer to determine if
an object is parented. Nuke it when the object is unparented to allow
for reuse of an object after unparenting.
Signed-off-by: Peter Crosthwaite
Signed-off-by: Andreas Färber
---
qom/object.c | 1 +
1
Hello Peter,
This is my QOM (devices) patch queue. Please pull.
Regards,
Andreas
Cc: Peter Maydell
Cc: Anthony Liguori
Cc: Peter Crosthwaite
The following changes since commit 53a259da5697ec8a82463161e2e32ff942a08bc2:
Merge remote-tracking branch
'remotes/awilliam/tags/vfio-pci-for-qemu
On 2014/6/30 19:28, Michael S. Tsirkin wrote:
On Mon, Jun 30, 2014 at 06:20:22PM +0800, Chen, Tiejun wrote:
On 2014/6/30 17:55, Michael S. Tsirkin wrote:
On Mon, Jun 30, 2014 at 05:38:21PM +0800, Chen, Tiejun wrote:
On 2014/6/30 17:05, Michael S. Tsirkin wrote:
On Mon, Jun 30, 2014 at 03:24:5
Hi Jan,
I use pci_setup_iommu() to setup a PCIIOMMUFunc for the q35 pci bus.
In the iommu_fn, I print out the devfn parameter and find out that it
sometimes will be -1. So what does it mean?
The detail code is here:
In mch_init() function, I write like this:
PCIBus *pci_bus = PCI_BUS(qdev_get_pare
On 2014/7/1 3:31, Ross Philipson wrote:
On 06/30/2014 03:22 PM, Stefano Stabellini wrote:
On Mon, 30 Jun 2014, Michael S. Tsirkin wrote:
On Mon, Jun 30, 2014 at 03:24:58PM +0800, Chen, Tiejun wrote:
On 2014/6/30 14:48, Michael S. Tsirkin wrote:
On Mon, Jun 30, 2014 at 10:51:49AM +0800, Chen,
On 2014/7/1 3:34, Stefano Stabellini wrote:
On Fri, 27 Jun 2014, Chen, Tiejun wrote:
On 2014/6/25 17:58, Chen, Tiejun wrote:
On 2014/6/25 17:44, Michael S. Tsirkin wrote:
On Wed, Jun 25, 2014 at 05:28:48PM +0800, Chen, Tiejun wrote:
On 2014/6/25 17:21, Michael S. Tsirkin wrote:
On Wed, Jun 2
On 2014/7/1 3:42, Stefano Stabellini wrote:
On Mon, 30 Jun 2014, Chen, Tiejun wrote:
On 2014/6/29 20:14, Michael S. Tsirkin wrote:
On Sun, Jun 29, 2014 at 03:56:10PM +0800, Chen, Tiejun wrote:
On 2014/6/27 19:26, Paolo Bonzini wrote:
Il 27/06/2014 10:34, Chen, Tiejun ha scritto:
So how to
On 2014/6/30 19:18, Michael S. Tsirkin wrote:
On Thu, Jun 19, 2014 at 05:53:51PM +0800, Tiejun Chen wrote:
Originally the reason to probe ISA bridge instead of Dev31:Fun0
is to make graphics device passthrough work easy for VMM, that
only need to expose ISA bridge to let driver know the real
har
The existing test whether "-lm" needs to be included or not is
insufficient as it reports false negative on Fedora20/ppc64.
As the result, qemu-nbd/qemu-io/qemu-img tools cannot compile.
This replaces sin() with log() in the test.
Signed-off-by: Alexey Kardashevskiy
---
The bug was triggered b
Now qemu only supports vhd type VHD_FIXED and VHD_DYNAMIC,
so qemu can't read snapshot volume of vhd, and can't
support other storage features of vhd file.
The RFC adds vhd type VHD_DIFFERENCING support for qemu.
Ding xiao (1):
Support vhd type VHD_DIFFERENCING
block/vpc.c | 302 +
Now qemu only supports vhd type VHD_FIXED and VHD_DYNAMIC,
so qemu can't read snapshot volume of vhd, and can't
support other storage features of vhd file.
this patch add read parent information in function
"vpc_open", read bitmap in "vpc_read", and change bitmap
in "vpc_write".
Signed-off-by: Di
1)“ it's an automated output of perl simply changing one calling convention
to another”.What do you mean... I
can not find the point :)
2) The problem is :
a.use QEMU to run linux-0.2.img with command qemu-system-i386
linux-0.2.img or sth. like that
b.hwclock ,and we get a date1(2014-07
On Tue, Jul 1, 2014 at 1:31 AM, Paolo Bonzini wrote:
> Il 30/06/2014 17:47, Ming Lei ha scritto:
>
>> From: Ming Lei
>>
>> This patch implements .bdrv_io_plug and .bdrv_io_unplug
>> callbacks for linux-aio Block Drivers, so that submitting
>> I/O at batch can be supported on linux-aio.
>>
>> Sign
From: Fabian Aggeler
If EL3 is using Aarch64 IRQ/FIQ masking is ignored in
all exception levels other than EL3 if SCR.{FIQ|IRQ} is
set to 1 (routed to EL3).
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
target-arm/cpu.h | 98 +---
From: Fabian Aggeler
Use MVBAR register as exception vector base address for
exceptions taken to CPU monitor mode.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
target-arm/cpu.h| 1 +
target-arm/helper.c | 15 +--
2 files changed
From: Fabian Aggeler
When EL3 is running in Aarch32 (or ARMv7 with Security Extensions)
IFAR and DFAR have a secure and a non-secure instance.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
-
v3 -> v4
- Revert to array-based notation of far_el in combination with v7
From: Fabian Aggeler
Implements SMC instruction in Aarch32 using the A32 syndrome. When executing
SMC instruction from monitor CPU mode SCR.NS bit is reset.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
target-arm/helper.c| 11 +++
ta
From: Sergey Fedorov
...from non-secure state.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Greg Bellows
---
target-arm/helper.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index
From: Fabian Aggeler
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
target-arm/helper.c | 24 ++--
1 file changed, 6 insertions(+), 18 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 4233ae3..456b7e7 100644
--- a/target-arm/helper.c
From: Fabian Aggeler
When EL3 is running in Aarch32 (or ARMv7 with Security Extensions)
PAR has a secure and a non-secure instance.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
-
v3 -> v4
- Fix par union/structure definition
Signed-off-by: Greg Bellows
---
target-a
From: Fabian Aggeler
arm_is_secure() function allows to determine CPU security state
if the CPU implements Security Extensions/EL3.
arm_is_secure_below_el3() returns true if CPU is in secure state
below EL3.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellow
From: Fabian Aggeler
Adds a dedicated function for IRQ and FIQ exceptions to determine
target_el and mode (Aarch32) according to tables in ARM ARMv8 and
ARM ARM v7.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
--
v3 -> v4
- Fixed arm_phys_excp_target_el() 0/0/0 case t
From: Fabian Aggeler
Add TTBR0 and maps secure/non-secure instance of ttbr0 and ttbr1
accordingly (translation table base register).
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
target-arm/cpu.h| 21 +++--
target-arm/helper.c | 46 +
From: Fabian Aggeler
Prepare for cp register banking by inserting every cp register twice,
once for secure world and once for non-secure world.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
target-arm/cpu.h | 14 +++---
target-arm/helper.c| 20 +++
From: Fabian Aggeler
When EL3 is running in Aarch32 (or ARMv7 with Security Extensions)
VBAR has a secure and a non-secure instance, which are mapped to
VBAR_EL1 and VBAR_EL3.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
v3 -> v4
- Fix vbar union/structure defini
From: Fabian Aggeler
Increasing banked_r13 and banked_r14 to store LR_mon and SP_mon (bank
index 7).
Signed-off-by: Fabian Aggeler
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Greg Bellows
---
target-arm/cpu.h | 4 ++--
target-arm/machine.c | 4 ++--
2 files changed, 4 insertions(+), 4
On 06/30/2014 05:16 PM, Eric Blake wrote:
> I'm trying to track down a core dump with the QMP drive-mirror command.
Looks like the bug is related to a base image that is not a multiple of
a cluster size.
>
> # in one terminal:
> cd /tmp
> rm -f base.img snap1.img snap2.img copy.img
>
> # base.i
From: Fabian Aggeler
Implements NSACR register with corresponding read/write functions
for ARMv7 and ARMv8.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
target-arm/cpu.h| 6 +
target-arm/helper.c | 68 +++
From: Fabian Aggeler
Set ARM_FEATURE_EL3 feature for CPUs that implement Security Extensions.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
target-arm/cpu.c | 4
1 file changed, 4 insertions(+)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index d77be99..46ee1fe 10064
On 06/30/2014 05:16 PM, Eric Blake wrote:
> I'm trying to track down a core dump with the QMP drive-mirror command.
Oh, and a followup question:
I discovered that if I try to use drive-mirror to a file that is not
already large enough, the job starts successfully but fails at the point
where it e
I'm trying to track down a core dump with the QMP drive-mirror command.
# in one terminal:
cd /tmp
rm -f base.img snap1.img snap2.img copy.img
# base.img <- snap1.img <- snap2.img; intentionally populating base.img
# with a qcow2 header, but treating it as raw data
qemu-img create -f qcow2 base.i
From: Fabian Aggeler
When EL3 is running in Aarch32 (or ARMv7 with Security Extensions)
DFSR has a secure and a non-secure instance.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
v3 -> v4
- Reverted esr/dfsr back to array-based notation as a union with v7 naming.
From: Fabian Aggeler
Implements SCTLR_EL3 and uses secure/non-secure instance when
needed.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
hw/arm/pxa2xx.c| 2 +-
target-arm/cpu.c | 5 ++--
target-arm/cpu.h | 13 -
target-arm/helper.c| 78 +++
From: Fabian Aggeler
When EL3 is running in Aarch32 (or ARMv7 with Security Extensions)
IFSR has a secure and a non-secure instance.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
target-arm/cpu.h| 10 +-
target-arm/helper.c | 9 +
2 files changed, 14 inser
From: Fabian Aggeler
When EL3 is running in Aarch32 (or ARMv7 with Security Extensions)
DACR has a secure and a non-secure instance.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
hw/arm/pxa2xx.c | 2 +-
target-arm/cpu.h| 13 +++--
target-arm/helper.c | 19
From: Fabian Aggeler
Prepare ARMCPRegInfo to support specifying two fieldoffsets per
register definition. This will allow us to keep one register
definition for banked registers (different offsets for secure/
non-secure world).
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
tar
From: Fabian Aggeler
Since TTBCR is banked we will bank c2_mask and c2_base_mask too. This
avoids recalculating them on switches from secure to non-secure world.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
target-arm/cpu.h| 10 --
target-arm/helper.c | 15 +++
From: Greg Bellows
This patch adds code to mark duplicate CP register registrations as NO_MIGRATE
to avoid duplicate migrations.
Signed-off-by: Greg Bellows
---
target-arm/helper.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target-arm/
From: Fabian Aggeler
Adds TCR_EL3 system register and makes existing TTBCR banked. Adjust
translation functions to use TCR/TTBCR instance depending on CPU state.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
target-arm/cpu.h| 11 ++-
target-arm/helper.c | 50 ++
From: Fabian Aggeler
Rename CSSELR (cache size selection register) and add secure
instance (Aarch32).
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
target-arm/cpu.h| 10 +-
target-arm/helper.c | 9 +
2 files changed, 14 insertions(+), 5 deletions(-)
diff
From: Sergey Fedorov
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
target-arm/cpu.h| 1 +
target-arm/helper.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 4625088..7aecb0f 100644
--- a/targe
From: Fabian Aggeler
When EL3 is running in Aarch32 (or ARMv7 with Security Extensions)
FCSEIDR, CONTEXTIDR, TPIDRURW, TPIDRURO and TPIDRPRW have a secure
and a non-secure instance.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
--
v3 -> v4
- Fix tpidrprw mapping
Signe
From: Fabian Aggeler
If EL3 is in Aarch32 state certain cp registers are banked (secure and
non-secure instance). When reading or writing to coprocessor registers
the following macros can be used. If the CPU is in monitor mode SCR.NS
bit determines which instance is going to be accessed.
- USE_S
From: Sergey Fedorov
This patch is based on idea found in patch at
git://github.com/jowinter/qemu-trustzone.git
f3d955c6c0ed8c46bc0eb10b634201032a651dd2 by
Johannes Winter .
This flag prevents QEMU from executing TCG code generated for other CPU
security state. It also allows to generate differe
From: Fabian Aggeler
SCR.{IRQ/FIQ} bits allow to route IRQ/FIQ exceptions to monitor CPU
mode. When taking IRQ exception to monitor mode FIQ exception is
additionally masked.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
target-arm/helper.c | 9 +
From: Fabian Aggeler
This patch extends arm_excp_unmasked() according to ARM ARMv7 and
ARM ARMv8 (all EL running in Aarch32) and adds comments.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
target-arm/cpu.h | 77
1 file
From: Fabian Aggeler
bits when modifying CPSR.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
v3 -> v4
- Fixed up conditions for ignoring CPSR.A/F updates by isolating to v7 and
checking for the existence of EL3 and non-existence of EL2.
Signed-off-by: Greg Bello
From: Greg Bellows
Updated Fabian's v3 patchset for review comments. This patchset includes
changes in support of the security extension on v7 aarch32 with hooks for later
enabling v8 aarch64.
The patches are built upon and therefore dependent on v3 of Xilinx's second
round of EL2/3 patches.
From: Fabian Aggeler
Make arm_current_pl() return PL3 for secure PL1 and monitor mode.
Increase MMU modes since mmu_index is directly infered from arm_
current_pl(). Changes assertion in arm_el_is_aa64() to allow EL3.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
target-arm/cp
From: Fabian Aggeler
Define a new ARM CP register info list for the ARMv7 Security Extension
feature. Register that list only for ARM cores with Security Extension/EL3
support. Moving Aarch32 SCR into Security Extension register group.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
On 06/30/2014 03:58 PM, Gary Jordan wrote:
> Hi Eric,
[please don't top-post in technical lists]
>
> Could I find a way for two guests in two hosts to communicate? Like qemu
> starts one vm in Host 1 and qemu also starts a vm in Host 2, the vm can
> share their memory. Is there some existed w
On 06/30/2014 10:34 AM, Gary Jordan wrote:
> Dear developers,
>
> I want to design a shared memory for Vm in qemu. So, I also need to design
> a mechanism to let two vms communicate. Is there already some module in
> Qemu ?
It sounds like you are asking about ivshmem, which has already been
discu
Hi Eric,
Could I find a way for two guests in two hosts to communicate? Like qemu
starts one vm in Host 1 and qemu also starts a vm in Host 2, the vm can
share their memory. Is there some existed way to do that, like remote IPC
in qemu?
Thanks for your reply.
---Gary
2014-06-30 17:08 GMT-04
Dear developers,
I want to design a shared memory for Vm in qemu. So, I also need to design
a mechanism to let two vms communicate. Is there already some module in
Qemu ?
I saw that qemu could support live migration. Can the vm also access the
previous machine after migration? Thanks.
Gary
Currently management softwares cannot know whether a qemu-ga command is
supported or not on the running platform until they actually execute it.
This patch disables unsupported commands at launch time of qemu-ga, so that
management softwares can check whether they are supported from 'enabled'
prope
If an array of mount point paths is specified as 'mountpoints' argument
of guest-fsfreeze-freeze-list, qemu-ga will only freeze the file systems
mounted on specified paths in Linux guests. Otherwise, it works as the
same way as guest-fsfreeze-freeze.
This would be useful when the host wants to crea
Add command to get mounted filesystems information in the guest.
The returned value contains a list of mountpoint paths and
corresponding disks info such as disk bus type, drive address,
and the disk controllers' PCI addresses, so that management layer
such as libvirt can resolve the disk backends.
Hi,
As patch 3/3 was missing in the last post, I'm resending this patchset.
===
This is v5 patch for qemu-ga to add functions to freeze specific file systems
mounted in a guest.
Changes since v4:
- PATCH 2: fix coding styles (spaces around operators)
make decode_mntname() more gener
On Mon, Jun 30, 2014 at 11:26:10AM -0700, Nishanth Aravamudan wrote:
[...]
> > > -if (i == nb_numa_nodes) {
> > > +if (i == max_numa_node) {
> > > for (i = 0; i < max_cpus; i++) {
> > > -set_bit(i, numa_info[i % nb_numa_nodes].node_cpu);
> > > +
> -Original Message-
> From: Alexander Graf [mailto:ag...@suse.de]
> Sent: Monday, June 30, 2014 1:22 PM
> To: Stalley, Sean; Peter Crosthwaite
> Cc: qemu-devel@nongnu.org
> Subject: Re: [Qemu-devel] Adding memory region without specifying address
>
>
> On 30.06.14 19:53, Stalley, Sean
Sparse node numbering occurs on powerpc in practice under PowerVM. In
order to emulate the same NUMA topology under qemu, the assumption that
NUMA nodes are linearly ordered has to be removed. qemu was recently
modified to reject requests for sparse NUMA node numbering.
Leverage the present field
On 06/30/2014 03:02 PM, Gary Jordan wrote:
> Hi,
> Does Qemu only use the QEMUFile to load the state of VM after migration?
Normally, yes. Migration must work as a one-way protocol in the common
case when used with default options.
There is a migration mode that uses RDMA which requires bi-direc
Hi,
Does Qemu only use the QEMUFile to load the state of VM after migration?
Is there a way for two vm guests to communicate like two threads or
processes?
Gary
On Mon, Jun 30, 2014 at 11:39:43AM -0700, Richard Henderson wrote:
> Looks good.
>
> I've split it up into a couple of smaller patches, made some sylistic tweaks
> and pushed it to
>
> git://github.com/rth7680/qemu.git axp-next
>
> I'm starting to do some testing now, but a glance though woul
Make phyreg_writeops responsible for actually writing their
respective phy registers. The only current instance of
phyreg_writeops is the set_phy_ctrl() function, which we modify
to actually write the register, while also correctly handling
reserved and self-clearing bits.
have_autoneg() does not
On 30.06.14 19:53, Stalley, Sean wrote:
Thanks for the quick response! Sorry for my belated reply...
-Original Message-
From: peter.crosthwa...@petalogix.com
[mailto:peter.crosthwa...@petalogix.com] On Behalf Of Peter Crosthwaite
Sent: Friday, June 27, 2014 6:26 PM
To: Stalley, Sean; A
On 30 Jun 2014, at 20:53, Lb peace wrote:
> If you use hwclock in guest os ,you will find the result of hwclock isn't
> changed after changing host os's clock.
> I find this issue is generated in this patch:
I find it hard to believe that the patch you mention is the problem,
as it's an autom
If you use hwclock in guest os ,you will find the result of hwclock isn't
changed after changing host os's clock.
I find this issue is generated in this patch:
http://lists.gnu.org/archive/html/qemu-devel/2013-08/msg03353.html
Before this patch,the result will be changed if you change host's clock
On Mon, 30 Jun 2014, Chen, Tiejun wrote:
> On 2014/6/29 20:14, Michael S. Tsirkin wrote:
> > On Sun, Jun 29, 2014 at 03:56:10PM +0800, Chen, Tiejun wrote:
> > > On 2014/6/27 19:26, Paolo Bonzini wrote:
> > > > Il 27/06/2014 10:34, Chen, Tiejun ha scritto:
> > > > >
> > > > >
> > > > > So how to s
On 06/30/2014 05:48 AM, Maria Kustova wrote:
> 'Overall fuzzer requirements' chapter contains the current product vision and
> features done and to be done. This chapter is still in progress.
>
> Signed-off-by: Maria Kustova
> ---
> tests/image-fuzzer/docs/image-fuzzer.txt | 176
> +
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