On Wed, Oct 22, 2014 at 08:39:59AM +0200, Markus Armbruster wrote:
> "Michael S. Tsirkin" writes:
>
> > On Tue, Oct 21, 2014 at 03:29:14PM +0200, Markus Armbruster wrote:
> >> "Michael S. Tsirkin" writes:
> >>
> >> > On Tue, Oct 21, 2014 at 02:22:41PM +0200, Markus Armbruster wrote:
> [...]
> >
Unfortunately this cannot be fixed. The way to go is to add a USB tablet
to the virtual machine. This will keep the two mouse cursors
synchronized.
** Changed in: qemu
Status: New => Won't Fix
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subsc
"Michael S. Tsirkin" writes:
> On Tue, Oct 21, 2014 at 03:29:14PM +0200, Markus Armbruster wrote:
>> "Michael S. Tsirkin" writes:
>>
>> > On Tue, Oct 21, 2014 at 02:22:41PM +0200, Markus Armbruster wrote:
[...]
>> >> My patch to get_maintainers.pl triggered a whole thread, while the
>> >> messa
On 10/22/2014 04:26 AM, john.liuli wrote:
> From: Li Liu
>
> qtest_log_fp should be inited before qemu_chr_add_handlers.
> If not the log dumped from callback functions may be lost.
>
> easy to reproduce it by command:
> "QTEST_LOG=1 QTEST_QEMU_BINARY=x86_64-softmmu/qemu-system-x86_64
> gtester
On Wed, Oct 22, 2014 at 12:06:18AM +0200, Paolo Bonzini wrote:
>
>
> On 10/21/2014 02:37 PM, Marcel Apfelbaum wrote:
> > ROM images must be loaded at startup. Usage of rombar=0 after that
> > is not allowed, but should not crash QEMU.
> >
> > Check that the device is not hotplugged before trying
On Tue, Oct 21, 2014 at 03:37:12PM +0300, Marcel Apfelbaum wrote:
> ROM images must be loaded at startup. Usage of rombar=0 after that
> is not allowed, but should not crash QEMU.
>
> Check that the device is not hotplugged before trying to
> insert the rom file.
>
> Signed-off-by: Marcel Apfelba
Introduce helper function acpi_set_cpu_present_bit() to simplify
acpi_cpu_plug_cb
and acpi_cpu_hotplug_init, so that we can keep bit setting in one place.
Signed-off-by: Gu Zheng
---
v6:
-using error_abort instead of local_err, so that we can gain the error report
before abort (suggested by I
Rename:
AcpiCpuHotplug_init --> acpi_cpu_hotplug_init
AcpiCpuHotplug_ops --> acpi_cpu_hotplug_ops
for better readability, just cleanup.
Reviewed-by: Igor Mammedov
Signed-off-by: Gu Zheng
---
hw/acpi/cpu_hotplug.c |4 ++--
hw/acpi/ich9.c|4 ++--
hw/acpi/piix4.c
Remove the unused CPU hot-plug notifier.
Reviewed-by: Igor Mammedov
Signed-off-by: Gu Zheng
---
v5:
-delete the caller of notifier_list_notify() in this patch.
include/sysemu/sysemu.h |3 ---
qom/cpu.c | 10 --
2 files changed, 0 insertions(+), 13 deletions(-)
dif
Update rtc_cmos in pc_cpu_plug() directly, instead of the notifier.
Reviewed-by: Igor Mammedov
Signed-off-by: Gu Zheng
---
v5:
-move CPU hot-plug notifier cleanup hunk into Patch 6/8.
v4:
-Make link property in PCMachine rather than the global
variables.
-Split out the removal of unused no
Add cpu hotplug handler to PC_MACHINE, which will perform the acpi
cpu hotplug callback via hotplug_handler API.
Reviewed-by: Igor Mammedov
Signed-off-by: Gu Zheng
---
v5:
-split the check out of acpi_dev block.
v3:
-deal with start up cpus in a more neat way as Igor suggested.
v2:
-just reba
Convert notifier based hotplug to hotplug_handler API,
and remove the unused AcpiCpuHotplug_add().
Reviewed-by: Igor Mammedov
Signed-off-by: Gu Zheng
---
v5:
-drop 'handle' from the comment and subject.
v2:
-remove the unused AcpiCpuHotplug_add().
hw/acpi/cpu_hotplug.c | 14 ++-
Convert notifier based hotplug to hotplug_handler API.
Reviewed-by: Igor Mammedov
Signed-off-by: Gu Zheng
---
v5:
-drop 'handle' from the comment and subject.
hw/acpi/ich9.c | 13 ++---
include/hw/acpi/ich9.h |1 -
2 files changed, 2 insertions(+), 12 deletions(-)
diff
Add cpu hotplug callback function (acpi_cpu_plug_cb) to match hotplug_handler
API.
Reviewed-by: Igor Mammedov
Signed-off-by: Gu Zheng
---
v4:
-convert CPUState *cpu to DeviceState *dev like it's done for other handlers
and do cast to CPU inside.
v2:
-add errp argument to catch error.
-retu
Previously we use cpu_added_notifiers to register cpu hotplug notifier callback
which is not able to pass/handle errors, so we switch it to unified hotplug
handler API which allows to pass errors and would allow to cancel device_add
in case of error.
Thanks very much for Igor's review and suggestio
Hello,
I am new to qemu development. I wanted to start a qemu process having a memory
region that is encrypted. This process will later run an application inside and
the necessary instructions will be emulated by the qemu.
I am finding hard time in getting to know the files I need to modify. Can
- fix file names that were changed by the commit
b707ab7 hw/xtensa: remove extraneous xtensa_ prefix from file names
- mark OpenCores 10/100 Mbit MAC model as maintained.
Signed-off-by: Max Filippov
---
MAINTAINERS | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/MAIN
From: Gonglei
bootdevice.c was created by me, and I wrote most of
the code in this file. And now I can maintain it,
I'd hope nobody object this.
Cc: Gerd Hoffmann
Signed-off-by: Gonglei
---
MAINTAINERS | 5 +
1 file changed, 5 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 20
Another small question. I noticed that all block drivers call block_init
("module_init") and qemu_system binary has the "--enable-modules" command
line option.
But does QEMU support building block drivers outside the main source tree
? And can I load a new block driver module into running QEMU
From: Li Liu
qtest_log_fp should be inited before qemu_chr_add_handlers.
If not the log dumped from callback functions may be lost.
easy to reproduce it by command:
"QTEST_LOG=1 QTEST_QEMU_BINARY=x86_64-softmmu/qemu-system-x86_64
gtester -k --verbose -m=quick tests/qdev-monitor-test"
The log "[
>Use local variable to bdrv_pwrite_sync L1 table,
>needless to make conversion of cached L1 table between
>big-endian and host style.
>
>Signed-off-by: Zhang Haoyu
>Reviewed-by: Max Reitz
>---
>v2 -> v3:
> - replace g_try_malloc0 with qemu_try_blockalign
> - copy the latest local L1 table back to
OK, thanks, there are multiple branches in upstream qemu. Sorry
for my original said, and I can only say: for upstream develop
master branch, it does not support microblaze.
Excuse me, I does not mainly focus on only using qemu, and I
also found another easier way for test microblaze toolchain (u
Good news for us! thank you for your work. :-)
Thanks
Send from Lenovo A788t.
Peter Maydell wrote:
>On 9 October 2014 15:00, Chen Gang wrote:
>> The related variables are useless, need be removed, or can not pass
>> microblaze building, after fix it, can build microblaze, successfully.
>>
>>
Public bug reported:
When installing/using OSX on QEMU, the mouse cursor is way out of whack
with the client VNC. It is possible to speed this up in the control
panel, but it is never quite in sync. Installing is a fun game of
trying to get the cursor where you want it to go.
** Affects: qemu
Current support for bus master (clearing OK bit) together with the need to
support guests which do not enable PCI bus mastering, leads to extra state in
VIRTIO_PCI_FLAG_BUS_MASTER_BUG bit, which isn't robust in case of cross-version
migration for the case when guests use the device before setting D
Low-hanging fruit...
Signed-off-by: Paolo Bonzini
---
MAINTAINERS | 7 +++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 4f56480..8b110aa 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -76,6 +76,7 @@ M: Richard Henderson
S: Maintained
F: target-alpha/
F: hw
On Tue, Oct 21, 2014 at 04:15:08PM +0200, Markus Armbruster wrote:
> >> We do have too may files lacking maintainers. See
> >>
> >> Subject: MAINTAINERS leaves too many files uncovered
> >> Date: Mon, 20 Oct 2014 11:19:44 +0200
> >> Message-ID: <87mw8rumhb@blackfin.pond.sub.org>
>
More work for the block device maintainers!
Signed-off-by: Paolo Bonzini
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 150dd07..24ca238 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -725,6 +725,7 @@ F: block/
F: hw/block/
F: qemu-img*
F: q
On Tue, Oct 21, 2014 at 03:34:46PM +0200, Markus Armbruster wrote:
> Paolo Bonzini writes:
>
> > On 10/20/2014 04:15 PM, Michael S. Tsirkin wrote:
> >> What do you want to happen in this case?
> >> Won't this cause even more patches to fall to the floor?
> >>
> >> The benefit seems marginal, the
On Tue, Oct 21, 2014 at 03:29:14PM +0200, Markus Armbruster wrote:
> "Michael S. Tsirkin" writes:
>
> > On Tue, Oct 21, 2014 at 02:22:41PM +0200, Markus Armbruster wrote:
> >> "Michael S. Tsirkin" writes:
> >>
> >> > On Tue, Oct 21, 2014 at 11:31:12AM +0200, Markus Armbruster wrote:
> >> >> "Mi
On Tue, Oct 21, 2014 at 09:07:40AM -0600, Alex Williamson wrote:
> On Tue, 2014-10-21 at 13:15 +0200, Alexander Graf wrote:
> >
> > On 21.10.14 11:35, Knut Omang wrote:
> > > On Tue, 2014-10-21 at 11:07 +0200, Alexander Graf wrote:
> > >>
> > >>
> > >>> Am 21.10.2014 um 07:26 schrieb Knut Omang :
Unfortunately, TCG files do not really have a maintainer yet.
But at least there will be fewer unmaintained files.
Signed-off-by: Paolo Bonzini
---
MAINTAINERS | 16
1 file changed, 16 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 206bf7e..70d58a5 100644
--- a/MAIN
On Di, 2014-10-21 at 20:11 +0100, Peter Maydell wrote:
> On 21 October 2014 19:31, Gerd Hoffmann wrote:
> > Looking them up in System.map finds me:
> >
> > c04eee18 T __loop_delay
> > c0868a28 T panic
> >
> > Ok, so the kernel came successfully though the uncompressing +
> > relocation + enable pa
On 10/21/2014 02:37 PM, Marcel Apfelbaum wrote:
> ROM images must be loaded at startup. Usage of rombar=0 after that
> is not allowed, but should not crash QEMU.
>
> Check that the device is not hotplugged before trying to
> insert the rom file.
I think it could also make sense to just ignore t
On 21 October 2014 22:33, Peter Maydell wrote:
> Suggestions:
...you might also try asking on kvm...@lists.cs.columbia.edu, which
is where the KVM/ARM kernel devs hang out, to see if somebody
else has seen this.
-- PMM
On 21 October 2014 22:15, Richard Jones wrote:
> I have now also tried virtio-blk and that doesn't work either. Same
> symptoms: no log messages at all (even with ignore_loglevel), and no
> disks appear.
>
>> Yeah, "regressed with this newer kernel" sounds more like a kernel
>> bug than a QEMU bu
I have now also tried virtio-blk and that doesn't work either. Same
symptoms: no log messages at all (even with ignore_loglevel), and no
disks appear.
> Yeah, "regressed with this newer kernel" sounds more like a kernel
> bug than a QEMU bug to me, especially if all the other virt devices
> still
On 21 October 2014 20:07, Richard Jones wrote:
> Public bug reported:
>
> kernel-3.18.0-0.rc1.git0.1.rwmj5.fc22.aarch64 (3.18 rc1 + some hardware
> enablement)
> qemu from git today
>
> When I create a guest with virtio-scsi disks, they don't show up inside the
> guest.
> Literally after the vir
Public bug reported:
kernel-3.18.0-0.rc1.git0.1.rwmj5.fc22.aarch64 (3.18 rc1 + some hardware
enablement)
qemu from git today
When I create a guest with virtio-scsi disks, they don't show up inside the
guest.
Literally after the virtio_mmio.ko and virtio_scsi.ko modules are loaded, there
are
no
On 21 October 2014 19:31, Gerd Hoffmann wrote:
> Looking them up in System.map finds me:
>
> c04eee18 T __loop_delay
> c0868a28 T panic
>
> Ok, so the kernel came successfully though the uncompressing +
> relocation + enable paging, but paniced before earlyprintk can print
> something.
>
> Guess I
Hi,
> > Any hints how to go on with debugging?
>
> Use the gdbstub to find out where the kernel is getting
> stuck? "Kernel produces no output" just means "we didn't
> get far enough through early boot for the kernel to start
> sending output to the UART. You might find it useful to
> turn on t
Hi Markus,
On Tue, Oct 21, 2014 at 10:17:17AM +0200, Markus Armbruster wrote:
> Wouter Verhelst writes:
> > On Mon, Oct 20, 2014 at 01:51:43PM +0200, Markus Armbruster wrote:
[...]
> >> Furthermore, STARTTLS is vulnerable to active attacks: if you can get
> >> between the peers, you can make them
On Tue, 2014-09-30 at 07:47 +0100, Eric Auger wrote:
> This patch removes all DPRINTF and replace them by trace points.
> A few DPRINTF used in error cases were transformed into error_report.
>
> Signed-off-by: Eric Auger
>
> ---
>
> - __func__ is removed since trace point name does the same jo
On Tue, Oct 21, 2014 at 10:35:06AM +0100, Daniel P. Berrange wrote:
> On Tue, Oct 21, 2014 at 12:10:39AM +0200, Wouter Verhelst wrote:
> > On Mon, Oct 20, 2014 at 01:56:43PM +0200, Florian Weimer wrote:
> > > I cannot comment on whether the proposed STARTTLS command is at the
> > > correct
> > > s
On 10/21/2014 02:51 AM, Max Reitz wrote:
> The bmap can be rather large (maximum blocks per image count:
> 0x3fff; the bmap has a size of block_count * sizeof(uint32_t) bytes,
> which makes 0xfffc bytes) and exceed INT_MAX. Using block layer
> functions which take a byte count as an int is
On 10/21/2014 02:51 AM, Max Reitz wrote:
> There are macros for these operations, so make use of them.
>
> Signed-off-by: Max Reitz
> ---
> block/vdi.c | 9 -
> 1 file changed, 4 insertions(+), 5 deletions(-)
>
> @@ -475,7 +474,7 @@ static int vdi_open(BlockDriverState *bs, QDict *opti
Added CP register info entries for the ARMv7 MAIR0/1 secure banks.
Signed-off-by: Greg Bellows
==
v5 -> v6
- Changed _el field variants to be array based
Signed-off-by: Greg Bellows
---
target-arm/cpu.h| 12 +++-
target-arm/helper.c | 8 +---
2 files changed, 16 inse
From: Fabian Aggeler
When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
FCSEIDR, CONTEXTIDR, TPIDRURW, TPIDRURO and TPIDRPRW have a secure
and a non-secure instance.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
==
v6 -> v7
- Fix linux-user/arm/target-cpu.
From: Fabian Aggeler
When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
IFAR and DFAR have a secure and a non-secure instance.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
-
v3 -> v4
- Revert to array-based notation of far_el in combination with v7
From: Fabian Aggeler
When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
PAR has a secure and a non-secure instance.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
==
v5 -> v6
- Changed _el field variants to be array based
- Merged VBAR and VBAR_EL1 reginfo
From: Fabian Aggeler
Adds TCR_EL3 system register and makes existing TTBCR banked. Adjust
translation functions to use TCR/TTBCR instance depending on CPU state.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
==
v5 -> v6
- Changed _el field variants to be array based
v4 -
From: Fabian Aggeler
When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
IFSR has a secure and a non-secure instance.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
target-arm/cpu.h| 10 +-
target-arm/helper.c | 9 +
2 files changed, 14 inser
From: Fabian Aggeler
Since TTBCR is banked we will bank c2_mask and c2_base_mask too. This
avoids recalculating them on switches from secure to non-secure world.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
==
v5 -> v6
- Switch to use distinct CPREG secure flags
v4 -> v
From: Fabian Aggeler
When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
DFSR has a secure and a non-secure instance.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
v3 -> v4
- Reverted esr/dfsr back to array-based notation as a union with v7 naming.
From: Fabian Aggeler
Add TTBR0 and maps secure/non-secure instance of ttbr0 and ttbr1
accordingly (translation table base register).
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
==
v5 -> v6
- Changed _el field variants to be array based
- Merged TTBR# and TTBR#_EL1 regin
From: Fabian Aggeler
Set ARM_FEATURE_EL3 feature for CPUs that implement Security Extensions.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
target-arm/cpu.c | 4
1 file changed, 4 insertions(+)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 63573c6..1e93d7e 10064
From: Fabian Aggeler
bits when modifying CPSR.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
v3 -> v4
- Fixed up conditions for ignoring CPSR.A/F updates by isolating to v7 and
checking for the existence of EL3 and non-existence of EL2.
Signed-off-by: Greg Bello
Hi,
> Retrieving file: /dtb-3.16.0-0.rc7.git1.1.fc22.armv7hl/sun7i-a20-bananapi.dtb
> 22335 bytes read in 2312 ms (8.8 KiB/s)
> Kernel image @ 0x4200 [ 0x00 - 0x5a8640 ]
> ## Flattened Device Tree blob at 4300
>Booting using the fdt blob at 0x4300
>Loading Ramdisk to 4e3d
Added additional NS-bit to CPREG hash encoding. Updated hash lookup
locations to specify hash bit currently set to non-secure.
Signed-off-by: Greg Bellows
==
v5 -> v6
- Globally replace Aarch# with AArch#
Signed-off-by: Greg Bellows
---
target-arm/cpu.h | 25 ++
From: Fabian Aggeler
Implements SCTLR_EL3 and uses secure/non-secure instance when
needed.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
==
v5 -> v6
- Changed _el field variants to be array based
- Consolidate SCTLR and SCTLR_EL1 reginfo entries
Signed-off-by: Greg Bello
From: Fabian Aggeler
SCR.{IRQ/FIQ} bits allow to route IRQ/FIQ exceptions to monitor CPU
mode. When taking IRQ exception to monitor mode FIQ exception is
additionally masked.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
target-arm/helper.c | 9 +
From: Fabian Aggeler
When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
DACR has a secure and a non-secure instance.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
hw/arm/pxa2xx.c | 2 +-
target-arm/cpu.h| 13 +++--
target-arm/helper.c | 19
From: Fabian Aggeler
Prepare for cp register banking by inserting every cp register twice,
once for secure world and once for non-secure world.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
==
v5 -> v6
- Fixed NS-bit number in the CPREG hash lookup from 27 to 29.
- Switch
From: Fabian Aggeler
Use MVBAR register as exception vector base address for
exceptions taken to CPU monitor mode.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
target-arm/cpu.h| 1 +
target-arm/helper.c | 15 +--
2 files changed
From: Fabian Aggeler
Implements SMC instruction in AArch32 using the A32 syndrome. When executing
SMC instruction from monitor CPU mode SCR.NS bit is reset.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
==
v5 -> v6
- Fixed PC offsetting for
From: Fabian Aggeler
Rename CSSELR (cache size selection register) and add secure
instance (AArch32).
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
==
v5 -> v6
- Changed _el field variants to be array based
- Switch to use distinct CPREG secure flags.
- Merged CSSELR and
From: Fabian Aggeler
Implements NSACR register with corresponding read/write functions
for ARMv7 and ARMv8.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
--
v4 -> v5
- Changed to use renamed arm_current_el()
Signed-off-by: Greg Bellows
---
From: Fabian Aggeler
Prepare ARMCPRegInfo to support specifying two fieldoffsets per
register definition. This will allow us to keep one register
definition for banked registers (different offsets for secure/
non-secure world).
Also added secure state tracking field and flags. This allows for
i
From: Fabian Aggeler
arm_is_secure() function allows to determine CPU security state
if the CPU implements Security Extensions/EL3.
arm_is_secure_below_el3() returns true if CPU is in secure state
below EL3.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellow
From: Sergey Fedorov
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
target-arm/cpu.h| 1 +
target-arm/helper.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index f9221a4..2202465 100644
--- a/targe
From: Fabian Aggeler
Define a new ARM CP register info list for the ARMv7 Security Extension
feature. Register that list only for ARM cores with Security Extension/EL3
support. Moving AArch32 SCR into Security Extension register group.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
From: Fabian Aggeler
If EL3 is in AArch32 state certain cp registers are banked (secure and
non-secure instance). When reading or writing to coprocessor registers
the following macros can be used.
- A32_BANKED macros are used for choosing the banked register based on provided
input security ar
From: Fabian Aggeler
Increasing banked_r13 and banked_r14 to store LR_mon and SP_mon (bank
index 7).
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
Reviewed-by: Peter Maydell
==
v5 -> v6
- Updated vmstate_arm_cpu versioning from 20 to 21
Signed-off-by: Greg Bellows
---
From: Fabian Aggeler
This patch extends arm_excp_unmasked() according to ARM ARMv7 and
ARM ARMv8 (all EL running in AArch32) and adds comments.
If EL3 is using AArch64 IRQ/FIQ masking is ignored in
all exception levels other than EL3 if SCR.{FIQ|IRQ} is
set to 1 (routed to EL3).
Signed-off-by:
Renamed the arm_current_pl CPU function to more accurately represent that it
returns the ARMv8 EL rather than ARMv7 PL.
Signed-off-by: Greg Bellows
Reviewed-by: Peter Maydell
==
v6 -> v7
- Fix comment
v5 -> v6
- Renamed DisasContext current_pl field to current_el
- Added comment to ar
From: Fabian Aggeler
Adds a dedicated function for IRQ and FIQ exceptions to determine
target_el and mode (AArch32) according to tables in ARM ARMv8 and
ARM ARM v7.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
==
v5 -> v6
- Removed unneeded arm_phys_excp_target_el() func
From: Sergey Fedorov
Reject switching to monitor mode from non-secure state.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
Reviewed-by: Edgar E. Iglesias
Reviewed-by: Peter Maydell
---
target-arm/helper.c | 2 ++
1 file changed, 2 insertions(+)
di
From: Fabian Aggeler
Make arm_current_el() return EL3 for secure PL1 and monitor mode.
Increase MMU modes since mmu_index is directly inferred from arm_
current_el(). Change assertion in arm_el_is_aa64() to allow EL3.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
Reviewed-by: Peter
From: Sergey Fedorov
This patch is based on idea found in patch at
git://github.com/jowinter/qemu-trustzone.git
f3d955c6c0ed8c46bc0eb10b634201032a651dd2 by
Johannes Winter .
The TBFLAG captures the SCR NS secure state at the time when a TB is created so
the correct bank is accessed on system reg
Version 7 of the ARM processor security extension (TrustZone) support.
This patchset includes changes to support the processor security extensions
on ARMv7 aarch32 with hooks for later enabling v8 aarch64/32.
Summary of changes from v6 -> v7:
- Fixed comment and commit message issues
- Updated lin
On 10/21/14 07:35, Michael S. Tsirkin wrote:
We have a bunch of modules in "Odd fixes"
status, scripts/get_maintainer.pl ignores that.
Reported-by: Gerd Hoffmann
Cc: Paolo Bonzini
Cc: Peter Maydell
Cc: Markus Armbruster
Signed-off-by: Michael S. Tsirkin
---
scripts/get_maintainer.pl | 2 +
On Tue, Oct 21, 2014 at 06:41:14PM +0800, Chen Gang wrote:
> On 10/21/14 12:37, Guenter Roeck wrote:
> > On 10/20/2014 08:23 AM, Chen Gang wrote:
> >> On 10/19/2014 10:58 PM, Guenter Roeck wrote:
> >>>
> >>> This doesn't use devicetree, but the configurations are known to be
> >>> working
> >>> wi
On 2014-10-20 at 16:48, Kevin Wolf wrote:
Am 20.10.2014 um 16:39 hat Max Reitz geschrieben:
On 20.10.2014 at 16:25, Kevin Wolf wrote:
Am 29.08.2014 um 23:40 hat Max Reitz geschrieben:
The size of a refblock entry is (in theory) variable; calculate
therefore the number of entries per refblock a
Add instructions of BO opcode format.
Add microcode generator functions gen_swap, gen_ldmst.
Add microcode generator functions gen_st/ld_preincr, which write back the
address after the memory access.
Add helper for circular and bit reverse addr mode calculation.
Add sign extended bitmask for BO_OF
Add instructions of B opcode format.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/translate.c | 27 +++
1 file changed, 27 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index fc89a43..830bcd0 10
Add instructions of ABS, ABSB opcode format.
Add microcode generator functions for ld/st of two 32bit reg as one 64bit value.
Add microcode generator functions for ldmst and swap.
Add helper ldlcx, lducx, stlcx and stucx.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
targ
Move FCX loading of save_context_ to caller functions, for STLCX, STUCX insn to
use those functions.
Move FCX storing of restore_context_ to caller functions, for LDLCX, LDUCX insn
to use those functions.
Remove do_raise_exception function, which caused clang to emit a warning.
Fix: save_context_
The following changes since commit 5f77ef69a195098baddfdc6d189f1b4a94587378:
glib: add compatibility interface for g_strcmp0() (2014-10-16 23:02:31 +0100)
are available in the git repository at:
https://github.com/bkoppelmann/qemu-tricore-upstream.git
tags/pull-tricore-20141021
for you to
Add instructions of BIT opcode format.
Add microcode generator functions gen_bit_1/2op to do 1/2 bit operations on the
last bit.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/translate.c | 312 +
1 file changed,
On 9 October 2014 15:00, Chen Gang wrote:
> The related variables are useless, need be removed, or can not pass
> microblaze building, after fix it, can build microblaze, successfully.
>
> The related configuration:
>
> ./configure --target-list="arm-softmmu,microblazeel-softmmu" --enable-fdt
>
On 10/21/2014 05:00 PM, Wei Huang wrote:
> No AMD CPUs support hyperthreading. When users select threads>1 in
> -smp option, QEMU fixes it by adjusting CPUID__0001_EBX and
> CPUID_8000_0008_ECX based on inputs (sockets, cores, threads);
> so guest VM can boot correctly. However it is still bett
On 10/21/2014 05:43 PM, Kevin Wolf wrote:
> Signed-off-by: Kevin Wolf
> ---
> MAINTAINERS | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index e54e3c6..c2d448d 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -713,6 +713,7 @@ F: block/
> F: hw/block/
>
Signed-off-by: Kevin Wolf
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index e54e3c6..c2d448d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -713,6 +713,7 @@ F: block/
F: hw/block/
F: qemu-img*
F: qemu-io*
+F: tests/qemu-iotests/
T: git git://re
On Tue, Oct 21, 2014 at 11:00:45AM -0400, Wei Huang wrote:
> No AMD CPUs support hyperthreading. When users select threads>1 in
> -smp option, QEMU fixes it by adjusting CPUID__0001_EBX and
> CPUID_8000_0008_ECX based on inputs (sockets, cores, threads);
> so guest VM can boot correctly. Howeve
On 10/20/2014 10:08 AM, Peter Maydell wrote:
On 20 October 2014 11:25, Stefan Hajnoczi wrote:
Hi,
At KVM Forum 2014 we discussed a patch checking bot that automates patch
format checking and smoke testing:
1. Did the patch submitter include Signed-off-by?
2. Does checkpatch.pl pass?
3. Does
Hi Gerd,
On 10/21/2014 03:33 PM, Gerd Hoffmann wrote:
> Hi,
>
> Played around with u-boot a bit, trying to get it work in qemu, so you
> don't have to hop through loops copying the kernel+initrd from the disk
> image to pass it to qemu on the command line.
>
> Guess why I'm asking here? No so
On 2014-10-21 at 17:11, Kevin Wolf wrote:
Am 21.10.2014 um 16:55 hat Max Reitz geschrieben:
On 2014-10-21 at 12:16, Max Reitz wrote:
On 2014-10-21 at 11:59, Kevin Wolf wrote:
Am 20.10.2014 um 16:35 hat Max Reitz geschrieben:
Because the old refcount structure will be leaked after having rebui
Am 21.10.2014 um 16:20 hat Max Reitz geschrieben:
> On 2014-10-21 at 16:12, Kevin Wolf wrote:
> >Am 20.10.2014 um 16:35 hat Max Reitz geschrieben:
> >>There are certain cases where repairing a qcow2 image might actually
> >>damage it further (or rather, where repairing it has in fact damaged it
> >
Patch posted. I will post another one for virt-manager.
-Wei
On 10/09/2014 05:16 PM, Eduardo Habkost wrote:
> On Thu, Oct 09, 2014 at 11:08:03PM +0200, Paolo Bonzini wrote:
>> Il 09/10/2014 22:22, Wei Huang ha scritto:
>>>
>>> Given that back-ward compatibility is a concern, will the following wo
Am 21.10.2014 um 16:55 hat Max Reitz geschrieben:
> On 2014-10-21 at 12:16, Max Reitz wrote:
> >On 2014-10-21 at 11:59, Kevin Wolf wrote:
> >>Am 20.10.2014 um 16:35 hat Max Reitz geschrieben:
> >>>Because the old refcount structure will be leaked after having rebuilt
> >>>it, we need to recalculate
1 - 100 of 225 matches
Mail list logo
