The local variable "type" in virtio_scsi_handle_ctl represents the tmf
command type from the guest and it has the same meaning as the
req->req.tmf.type. However, before the invoking of virtio_scsi_parse_req
the req->req.tmf.type doesn't has the correct value(just initialized to
zero). Therefore, we
Hi Peter,
Based on our discussion, I looked into a table lookup approach to replace
the arm_phys_excp_target_el() as we discussed. I have something working
but still need to verify it is 100% correct. Before I went much further, I
thought I'd share my findings.
In order to do the table in a way
The first program header does not necessarily start at offset 0. This change
corresponds to what the Linux kernel does in load_elf_binary().
Signed-off-by: Jonas Maebe
---
linux-user/elfload.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/linux-user/elfload.c b/linux-user/e
On 10/24/2014 11:58 PM, Michael Tokarev wrote:
> My 4.1.11 version tries to open /var/log/samba/log.smbd.bin file and
> gives up. After I created that file and chowned it to me it works.
(that .bin comes from /me renaming smbd to smbd.bin to run it under
strace from a tiny shell wrapper under or
It looks like smbd always logs to /var/log/samba/log.$progname
even if config file specifies different logfile -- when it needs
to log something before completing reading the config file. But
if it can't open it for writing, it fails and exits. Tell smbd
to use our temp dir as logbase (-l option)
On 10/24/2014 10:29 PM, Michael Tokarev wrote:
> On 10/24/2014 08:55 PM, Jan Kiszka wrote:
>> Hi Michael,
>>
>> writing to you as you provided a fix for the last related issue:
>>
>> I just noticed that the samba-based share is broken again with smbd
>> version 4.1.11. Tried to look briefly at it,
On 10/21/2014 12:10 AM, Gonglei wrote:
There is a problem.
1. Qemu receive the "eject" command.
2. Runs "eject_request_cb" when an eject request is issued from the
monitor, the tray
is closed, and the medium is locked. But the drive is not closed.
3. Guest agree
On 10/24/2014 08:55 PM, Jan Kiszka wrote:
> Hi Michael,
>
> writing to you as you provided a fix for the last related issue:
>
> I just noticed that the samba-based share is broken again with smbd
> version 4.1.11. Tried to look briefly at it, realized that it is a
> permission thing (different e
Hi everyone!
I'm new here.
Well, my doubt is: Which method/function is the responsible to set time and
date when I start a VM? I know there is some structures such as QEMUClock,
QEMUTimer, but I'm don't know yet who create it based on UTC and localtime,
for example. Can anyone explain the steps to
From: Stefan Berger
Create the TCPA log in a separate file rather than allocating
ACPI table memory for it.
Signed-off-by: Stefan Berger
---
hw/i386/acpi-build.c | 22 +++---
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-buil
I see this went by:
Il 07/10/2014 12:29, Dr. David Alan Gilbert ha scritto:
> You mean something like this (untested) ?
>
> if (mis->postcopy_ram_state != POSTCOPY_RAM_INCOMING_NONE) {
> if (mis->postcopy_ram_state == POSTCOPY_RAM_INCOMING_ADVISE) {
> /*
>* Where a mi
Hi Michael,
writing to you as you provided a fix for the last related issue:
I just noticed that the samba-based share is broken again with smbd
version 4.1.11. Tried to look briefly at it, realized that it is a
permission thing (different error when qemu runs as root) but also some
more nasty pr
On 21 October 2014 17:55, Greg Bellows wrote:
> From: Sergey Fedorov
>
> This patch is based on idea found in patch at
> git://github.com/jowinter/qemu-trustzone.git
> f3d955c6c0ed8c46bc0eb10b634201032a651dd2 by
> Johannes Winter .
>
> The TBFLAG captures the SCR NS secure state at the time when
On Thu, Oct 23, 2014 at 04:34:46PM +0200, Paolo Bonzini wrote:
> On 10/23/2014 05:02 AM, Chao Peng wrote:
> > Add AVX512 feature bits, register definition and corresponding
> > xsave/vmstate support.
> >
> > Signed-off-by: Chao Peng
> > ---
> > target-i386/cpu.c | 10 --
> > target-i38
On 21 October 2014 17:55, Greg Bellows wrote:
> From: Fabian Aggeler
>
> If EL3 is in AArch32 state certain cp registers are banked (secure and
> non-secure instance). When reading or writing to coprocessor registers
> the following macros can be used.
>
> - A32_BANKED macros are used for choosin
On 10/24/2014 07:57 AM, Max Reitz wrote:
> Add a test for qcow2's fast bdrv_make_empty implementation on images
> without internal snapshots.
>
> Signed-off-by: Max Reitz
> ---
> tests/qemu-iotests/098 | 82
> ++
> tests/qemu-iotests/098.out | 52
On 21 October 2014 17:55, Greg Bellows wrote:
> From: Fabian Aggeler
>
> Adds a dedicated function for IRQ and FIQ exceptions to determine
> target_el and mode (AArch32) according to tables in ARM ARMv8 and
> ARM ARM v7.
>
> Signed-off-by: Fabian Aggeler
> Signed-off-by: Greg Bellows
This seem
On 21 October 2014 17:55, Greg Bellows wrote:
> From: Fabian Aggeler
>
> This patch extends arm_excp_unmasked() according to ARM ARMv7 and
> ARM ARMv8 (all EL running in AArch32) and adds comments.
>
> If EL3 is using AArch64 IRQ/FIQ masking is ignored in
> all exception levels other than EL3 if
On 10/24/2014 07:57 AM, Max Reitz wrote:
> Introduce a new parameter for qemu-img commit which may be used to
> explicitly specify the backing file into which an image should be
> committed if the backing chain has more than a single layer.
>
> Signed-off-by: Max Reitz
> ---
> qemu-img-cmds.hx |
On 10/24/2014 07:57 AM, Max Reitz wrote:
> qemu-img should use QMP commands whenever possible in order to ensure
> feature completeness of both online and offline image operations. As
> qemu-img itself has no access to QMP (since this would basically require
> just everything being linked into qemu
On 23/10/2014 17:15, Richard Henderson wrote:
> [3] Hello, MIPS. Leon, the test for mips is (now) incorrect:
>
> if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0)
> break;
>
> may never succeed for mips16 and micromips.
Indeed, this test doesn't look right (although I'm not sure w
On Thu, Oct 23, 2014 at 11:02:43AM +0800, Chao Peng wrote:
> Add AVX512 feature bits, register definition and corresponding
> xsave/vmstate support.
>
> Signed-off-by: Chao Peng
> ---
[...]
> @@ -745,6 +829,9 @@ VMStateDescription vmstate_x86_cpu = {
> }, {
> .vmsd = &vmstat
On 10/24/2014 07:57 AM, Max Reitz wrote:
> As of a follow-up patch to this one, the length of a mirror block job
> will no longer directly depend on the size of the block device;
> therefore, drop these checks from this test. Instead, just check whether
> the final offset equals the block job lengt
On 10/24/2014 05:00 AM, Marc Marà wrote:
El Thu, 23 Oct 2014 18:49:03 -0400
John Snow escribió:
Reviewed-by: John Snow
Did you mean this for the v2, which has the extra free?
Marc
Yes. No more late-night replies to patches :\
On 10/24/2014 07:57 AM, Max Reitz wrote:
> bdrv_make_empty() is currently only called if the current image
> represents an external snapshot that has been committed to its base
> image; it is therefore unlikely to have internal snapshots. In this
> case, bdrv_make_empty() can be greatly sped up by
On 24/10/2014 13:42, Leon Alrae wrote:
In Revision 3 of the architecture, the RI and XI bits were added to the TLB
to enable more secure access of memory pages. These bits (along with the Dirty
bit) allow the implementation of read-only, write-only, no-execute access
policies for mapped pages.
S
On 24/10/2014 15:16, Leon Alrae wrote:
On 15/10/2014 13:24, Yongbok Kim wrote:
On 08/07/2014 08:57, Leon Alrae wrote:
In Revision 3 of the architecture, the RI and XI bits were added to
the TLB
to enable more secure access of memory pages. These bits (along with
the Dirty
bit) allow the impleme
On 15/10/2014 13:24, Yongbok Kim wrote:
>
> On 08/07/2014 08:57, Leon Alrae wrote:
>> In Revision 3 of the architecture, the RI and XI bits were added to
>> the TLB
>> to enable more secure access of memory pages. These bits (along with
>> the Dirty
>> bit) allow the implementation of read-only, w
On Fri, Oct 24, 2014 at 10:38:39AM +0200, Cornelia Huck wrote:
> On Fri, 24 Oct 2014 00:42:20 +0300
> "Michael S. Tsirkin" wrote:
>
> > On Tue, Oct 07, 2014 at 04:39:56PM +0200, Cornelia Huck wrote:
> > > This patchset aims to get us some way to implement virtio-1 compliant
> > > and transitional
On 10/24/2014 04:58 AM, Max Reitz wrote:
> It should not be happening, but it is possible to truncate an image
> outside of qemu while qemu is running (or any of the qemu tools using
> the block layer. raw_co_get_block_status() should not break then.
>
> While touching this test, replace the exist
On 10/24/2014 01:06 AM, Wen Congyang wrote:
> Introduce a "xen-load-devices-state" QAPI command that can be used to load
> the state of all devices, but not the RAM or the block devices of the
> VM.
>
> We only have hmp commands savevm/loadvm, and qmp commands
> xen-save-devices-state.
>
> We use
On Fri, 24 Oct 2014 13:42:16 +0100
Leon Alrae wrote:
> New MIPS features depend on the access type and enum is more convenient than
> using the numbers directly.
>
> Signed-off-by: Leon Alrae
> ---
> include/exec/cpu-common.h | 6 ++
> softmmu_template.h| 26 --
On Fri, Oct 24, 2014 at 02:37:08PM +0200, Cornelia Huck wrote:
> On Fri, 24 Oct 2014 10:38:39 +0200
> Cornelia Huck wrote:
>
> > On Fri, 24 Oct 2014 00:42:20 +0300
> > "Michael S. Tsirkin" wrote:
> >
> > > On Tue, Oct 07, 2014 at 04:39:56PM +0200, Cornelia Huck wrote:
> > > > This patchset aims
As different image formats most probably map guest addresses to
different host addresses, add a filter to filter the host addresses out;
also, the image filename should be filtered.
Signed-off-by: Max Reitz
Reviewed-by: Eric Blake
Reviewed-by: Kevin Wolf
---
tests/qemu-iotests/common.filter |
qemu-img should use QMP commands whenever possible in order to ensure
feature completeness of both online and offline image operations. As
qemu-img itself has no access to QMP (since this would basically require
just everything being linked into qemu-img), imitate QMP's
implementation of block-comm
Add a test for qcow2's fast bdrv_make_empty implementation on images
without internal snapshots.
Signed-off-by: Max Reitz
---
tests/qemu-iotests/098 | 82 ++
tests/qemu-iotests/098.out | 52 +
tests/qemu-iotests/group
Add a test for qemu-img commit on backing chains with more than two
images. This test also checks whether the top image is emptied (unless
this is prevented by specifying either -d or -b) and does therefore not
work for qed and vmdk which requires it to be separate from 020.
Signed-off-by: Max Rei
When a block job signals readiness, this is currently reported only
through QMP. If qemu wants to use block jobs for internal tasks, there
needs to be another way to correctly detect when a block job may be
completed.
For this reason, introduce a bool "ready" which is set when the block
job may be
After the top image has been committed, it should be emptied unless
specified otherwise.
Signed-off-by: Max Reitz
Reviewed-by: Eric Blake
Reviewed-by: Kevin Wolf
---
qemu-img-cmds.hx | 4 ++--
qemu-img.c | 34 +++---
qemu-img.texi| 6 +-
3 files chan
Implement progress output for the commit command by querying the
progress of the block job.
Signed-off-by: Max Reitz
Reviewed-by: Eric Blake
Reviewed-by: Kevin Wolf
---
qemu-img-cmds.hx | 4 ++--
qemu-img.c | 23 +--
qemu-img.texi| 2 +-
3 files changed, 24 inse
Introduce a new parameter for qemu-img commit which may be used to
explicitly specify the backing file into which an image should be
committed if the backing chain has more than a single layer.
Signed-off-by: Max Reitz
---
qemu-img-cmds.hx | 4 ++--
qemu-img.c | 32 +++
As of a follow-up patch to this one, the length of a mirror block job
will no longer directly depend on the size of the block device;
therefore, drop these checks from this test. Instead, just check whether
the final offset equals the block job length.
As 041 uses the wait_until_completed function
Implement block_job_complete_sync() by doing the exact same thing as
block_job_cancel_sync() does, only with calling block_job_complete()
instead of block_job_cancel().
Signed-off-by: Max Reitz
Reviewed-by: Kevin Wolf
---
blockjob.c | 39 ---
in
Normally, discarded sectors should read back as zero. However, there are
cases in which a sector (or rather cluster) should be discarded as if
they were never written in the first place, that is, reading them should
fall through to the backing file again.
Signed-off-by: Max Reitz
Reviewed-by: Eri
Instead of taking the total length of the block device as the block
job's length, use the number of dirty sectors. The progress is now the
number of sectors mirrored to the target block device. Note that this
may result in the job's length increasing during operation, which is
however in fact desir
bdrv_make_empty() is currently only called if the current image
represents an external snapshot that has been committed to its base
image; it is therefore unlikely to have internal snapshots. In this
case, bdrv_make_empty() can be greatly sped up by emptying the L1 and
refcount table (while having
Implement this function by making all clusters in the image file fall
through to the backing file (by using the recently extended discard).
Signed-off-by: Max Reitz
Reviewed-by: Eric Blake
Reviewed-by: Kevin Wolf
---
block/qcow2.c | 27 +++
1 file changed, 27 insertions
qemu-img should use QMP commands whenever possible in order to ensure
feature completeness of both online and offline image operations. For
the "commit" command, this is relatively easy, so implement it first
(in the hope that indeed others will follow).
As qemu-img does not have access to QMP (du
On Fri, Oct 24, 2014 at 03:36:20PM +0800, Chen, Tiejun wrote:
> >I think the point was mostly to reserve 1f to prevent
> >devices from using it.
> >As we populate slots in order it doesn't seem to important ...
>
> If we populate slot at !1f GFX driver can't find this ISA bridge.
Right, but I mea
>>virtio-blk and virtio-scsi emulation only runs in 1 thread at a time.
>>It is currently not possible to achieve true multiqueue from guest,
>>through QEMU, and down to the host.
>>
>>This is what the final slides in my presentation were about.
Ok Thanks !
>>Regarding Ceph, do you know why it b
On 15 October 2014 21:30, Peter Maydell wrote:
> Signed-off-by: Peter Maydell
> ---
> Update the 'general project admin' section to include me as
> well as Anthony, given that I've been in practice doing a
> bunch of said admin, and the general consensus at the QEMU
> Summit yesterday seemed to t
On 16 October 2014 16:11, Aurelien Jarno wrote:
> On Thu, Oct 16, 2014 at 12:38:07PM +0100, Leon Alrae wrote:
>> Add myself to the maintainer list for MIPS guest cores and update the status
>> from "Odd Fixes" to "Maintained".
>>
>> Signed-off-by: Leon Alrae
>> ---
>> MAINTAINERS | 3 ++-
>> 1 f
On 22 October 2014 14:00, Leon Alrae wrote:
> Signed-off-by: Leon Alrae
> ---
> target-mips/op_helper.c | 12 ++--
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
> index 5204ed8..9ec548c 100644
> --- a/target-mips/op_h
On 24/10/2014 10:35, Yongbok Kim wrote:
> Hi,
>
> On 22/10/2014 12:35, James Hogan wrote:
>> +union wr_t {
>> +int8_t b[MSA_WRLEN/8];
>> +int16_t h[MSA_WRLEN/16];
>> +int32_t w[MSA_WRLEN/32];
>> +int64_t d[MSA_WRLEN/64];
>> This is incorrect on a big endian host. The least signifi
Stefan Hajnoczi writes:
> On Thu, Oct 23, 2014 at 02:16:37PM +0200, Markus Armbruster wrote:
>> "Need BlockBackend" has been a recurring theme for a long time. It's
>> finally on master now. Plenty of work left to do. Let's coordinate
>> next steps to avoid duplicate work.
>
> Great job. Than
ble in the git repository at:
>
>
> git://git.linaro.org/people/pmaydell/qemu-arm.git
> tags/pull-target-arm-20141024
>
> for you to fetch changes up to dbe9d1636787dd226d3f9a61c07fbc27e0db5bbf:
>
> target-arm: A32: Em
In Release 6 not all the values are allowed to be written to a register.
If the value is not valid or unsupported then it should stay unchanged.
For pre-R6 the existing behaviour has been changed only for CP0_Index register
as the current implementation does not seem to be correct - it looks like
Release 6 limits the number of cases where software can cause UNDEFINED or
UNPREDICTABLE behaviour. In this case, when accessing reserved / unimplemented
CP0 register, writes are ignored and reads return 0.
In pre-R6 the behaviour is not specified, but generating RI exception is not
what the real
When conditional compact branch is encountered decode one more instruction in
current translation block - that will be forbidden slot. Instruction in
forbidden slot will be executed only if conditional compact branch is not taken.
Any control transfer instruction (CTI) which are branches, jumps, E
Signed-off-by: Leon Alrae
Reviewed-by: Yongbok Kim
---
target-mips/cpu.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 6367d8c..3b975eb 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -790,7 +790,8 @@ static inline voi
SDBBP instruction Reserved Instruction control. The purpose of this field is
to restrict availability of SDBBP to kernel mode operation.
If the bit is set then SDBBP instruction can only be executed in kernel mode.
User execution of SDBBP will cause a Reserved Instruction exception.
Additionally
BadInstr Register (CP0 Register 8, Select 1)
The BadInstr register is a read-only register that capture the most recent
instruction which caused an exception.
BadInstrP Register (CP0 Register 8, Select 2)
The BadInstrP register contains the prior branch instruction, when the
faulting instruction i
In Revision 3 of the architecture, the RI and XI bits were added to the TLB
to enable more secure access of memory pages. These bits (along with the Dirty
bit) allow the implementation of read-only, write-only, no-execute access
policies for mapped pages.
Signed-off-by: Leon Alrae
---
target-mip
An Execute-Inhibit exception occurs when the virtual address of an instruction
fetch matches a TLB entry whose XI bit is set. This exception type can only
occur if the XI bit is implemented within the TLB and is enabled, this is
denoted by the PageGrain XIE bit.
An Read-Inhibit exception occurs wh
Signed-off-by: Leon Alrae
---
target-mips/cpu.h | 2 +-
target-mips/machine.c | 26 +-
2 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 4687f4f..c66a725 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@
For Standard TLB configuration (Config.MT=1):
TLBINV invalidates a set of TLB entries based on ASID. The virtual address is
ignored in the entry match. TLB entries which have their G bit set to 1 are not
modified.
TLBINVF causes all entries to be invalidated.
Single TLB entry can be marked as in
New MIPS features depend on the access type and enum is more convenient than
using the numbers directly.
Signed-off-by: Leon Alrae
---
include/exec/cpu-common.h | 6 ++
softmmu_template.h| 26 --
2 files changed, 22 insertions(+), 10 deletions(-)
diff --git
Signed-off-by: Leon Alrae
Reviewed-by: Yongbok Kim
---
target-mips/helper.c | 21 ++---
1 file changed, 10 insertions(+), 11 deletions(-)
diff --git a/target-mips/helper.c b/target-mips/helper.c
index fe16820..1c9e69d 100644
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
Signed-off-by: Leon Alrae
Reviewed-by: Yongbok Kim
---
target-mips/translate_init.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index bcfc46a..0b70d05 100644
--- a/target-mips/translate_init.c
+++ b/t
This is the next version of patchset containing mainly MIPS64R6 Privileged
Resource Architecture changes and it complements the existing MIPS64R6
support in QEMU.
This patchset is concatenated from the following series which have been on
the mailing list for a while:
http://lists.gnu.org/archive/h
PageGrain needs rw bitmask which differs between MIPS architectures.
In pre-R6 if RIXI is supported, PageGrain.XIE and PageGrain.RIE are writeable,
whereas in R6 they are read-only 1.
On MIPS64 mtc0 instruction left shifts bits 31:30 for MIPS32 backward
compatiblity, therefore there are separate m
KScratch Registers (CP0 Register 31, Selects 2 to 7)
The KScratch registers are read/write registers available for scratch pad
storage by kernel mode software. They are 32-bits in width for 32-bit
processors and 64-bits for 64-bit processors.
CP0Config4.KScrExist[2:7] bits indicate presence of CP
On Fri, 24 Oct 2014 10:38:39 +0200
Cornelia Huck wrote:
> On Fri, 24 Oct 2014 00:42:20 +0300
> "Michael S. Tsirkin" wrote:
>
> > On Tue, Oct 07, 2014 at 04:39:56PM +0200, Cornelia Huck wrote:
> > > This patchset aims to get us some way to implement virtio-1 compliant
> > > and transitional devi
On 10/24/2014 01:12 PM, Eduardo Habkost wrote:
>> > I think we can keep the macros. The actual cleanup would be to have a
>> > single member for the 32 512-bit ZMM registers, instead of splitting
>> > xmm/ymmh/zmmh/zmm_hi16. This will get rid of the YMM_* and ZMM_*
>> > registers. However, we
From: Ard Biesheuvel
Move the registering of CPU reset handlers to before the point where
we leave the function in the -bios (not -kernel) case, so CPU reset
works correctly with -bios as well.
Signed-off-by: Ard Biesheuvel
Signed-off-by: Peter Maydell
---
hw/arm/boot.c | 17 -
On Thu, Oct 23, 2014 at 02:16:37PM +0200, Markus Armbruster wrote:
> "Need BlockBackend" has been a recurring theme for a long time. It's
> finally on master now. Plenty of work left to do. Let's coordinate
> next steps to avoid duplicate work.
Great job. Thanks for sending this email. I have
From: Chen Gang
The instructions-a64.h header defines a number of floating point
constants whose initializers are function calls. gcc 5 will warn
if these constants are not used by the C or C++ file which includes
the header, because they imply a runtime cost. Since for the files
QEMU uses from l
Update our copy of libvixl to upstream 1.6. There are no
changes of any particular interest to QEMU, so this is simply
keeping up with current upstream.
Signed-off-by: Peter Maydell
Message-id: 1412091418-25744-1-git-send-email-peter.mayd...@linaro.org
---
disas/arm-a64.cc |
From: Claudio Fontana
check if the first cpu is an armv8 cpu, and if so, put
arm,armv8-timer in the compatible string list.
Note that due to this check, this patch moves the creation
of the timer fdt node to after the cpu creation loop.
Signed-off-by: Claudio Fontana
Message-id: 1411736960-242
From: Fabian Aggeler
arm_is_secure() function allows to determine CPU security state
if the CPU implements Security Extensions/EL3.
arm_is_secure_below_el3() returns true if CPU is in secure state
below EL3.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellow
From: Markus Armbruster
This command lists PCMCIA sockets and cards. Only a few ARM boards
have sockets (akita, borzoi, connex, mainstone, spitz, terrier, tosa,
verdex, z2), the only card is the DSCM-1 Hitachi Microdrive (qdev
"microdrive"), and it is only inserted during machine init, if ev
From: KONRAD Frederic
This removes num_irq parameter from gic_init_irqs_and_distributor as it is not
used.
Signed-off-by: KONRAD Frederic
Message-id: 1412859651-15060-1-git-send-email-fred.kon...@greensocs.com
Signed-off-by: Peter Maydell
---
hw/intc/arm_gic.c | 4 ++--
hw/intc/armv7m_nv
From: Greg Bellows
Renamed the arm_current_pl CPU function to more accurately represent that it
returns the ARMv8 EL rather than ARMv7 PL.
Signed-off-by: Greg Bellows
Reviewed-by: Peter Maydell
Message-id: 1413910544-20150-5-git-send-email-greg.bell...@linaro.org
[PMM: fixed a minor merge reso
On 23 October 2014 21:42, Kevin Wolf wrote:
> The following changes since commit e40830afa1cff3ffdc37bdfdd40d80860074636c:
>
> Merge remote-tracking branch 'remotes/mdroth/tags/qga-pull-2014-10-22-tag'
> into staging (2014-10-22 21:42:33 +0100)
>
> are available in the git repository at:
>
>
>
From: Sergey Fedorov
Reject switching to monitor mode from non-secure state.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
Reviewed-by: Edgar E. Iglesias
Reviewed-by: Peter Maydell
Message-id: 1413910544-20150-4-git-send-email-greg.bell...@linaro.or
From: Fabian Aggeler
Increasing banked_r13 and banked_r14 to store LR_mon and SP_mon (bank
index 7).
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
Reviewed-by: Peter Maydell
Message-id: 1413910544-20150-2-git-send-email-greg.bell...@linaro.org
Signed-off-by: Peter Maydell
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ta
From: Fabian Aggeler
Implements SMC instruction in AArch32 using the A32 syndrome. When executing
SMC instruction from monitor CPU mode SCR.NS bit is reset.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
Message-id: 1413910544-20150-7-git-send-email-gr
From: "Dr. David Alan Gilbert"
This looks like an old merge error and should have no effect.
(Build tested only)
Found by Coccinelle using Julia Lawall's script:
https://lkml.org/lkml/2014/8/23/128
Signed-off-by: Dr. David Alan Gilbert
Message-id: 1414055855-6688-1-git-send-email-dgilb...@redh
From: Rob Herring
Add support for handling PSCI calls in system emulation. Both version
0.1 and 0.2 of the PSCI spec are supported. Platforms can enable support
by setting the "psci-conduit" QOM property on the cpus to SMC or HVC
emulation and having a PSCI binding in their dtb.
Signed-off-by: R
SMC must UNDEF if EL3 is not implemented; similarly HVC UNDEFs
if EL2 is not implemented. Move the handling of this from
translate-a64.c into the pre_smc and pre_hvc helper functions.
This is necessary because use of these instructions for PSCI
takes precedence over this UNDEF case, and we can't te
The ARM ARM requires that the FPINST and FPINST2 VFP control
registers are not accessible to code at EL0. We were already
correctly implementing this for reads of these registers; add
the missing check for the write code path.
Reported-by: Laurent Desnogues
Signed-off-by: Peter Maydell
Reviewed-
From: Rob Herring
User mode emulation should never get interrupts and thus should not
use the system emulation exception handler function. Remove the reference,
and '#ifndef USER_MODE_ONLY' the function itself as well, so that we can add
system mode only functionality to it.
Signed-off-by: Rob H
From: Ard Biesheuvel
This adds some PSCI function IDs and symbolic return codes that are needed
to implement PSCI emulation in TCG mode.
Reviewed-by: Peter Maydell
Signed-off-by: Ard Biesheuvel
Signed-off-by: Peter Maydell
Message-id: 1412865028-17725-4-git-send-email-peter.mayd...@linaro.org
From: Rob Herring
Add tracking of cpu power state in order to support powering off of
cores in system emuluation. The initial state is determined by the
start-powered-off QOM property.
Signed-off-by: Rob Herring
Reviewed-by: Peter Maydell
Signed-off-by: Ard Biesheuvel
Signed-off-by: Peter May
From: Rob Herring
Now that we have PSCI emulation, enable it for the virt platform.
This simplifies the virt machine a bit now that PSCI no longer
needs to be a KVM only feature.
Signed-off-by: Rob Herring
Signed-off-by: Ard Biesheuvel
Signed-off-by: Peter Maydell
Message-id: 1412865028-17725
The DZP bit in the DCZID system register should be set if
the control bits which prohibit use of the DC ZVA instruction
have been set (it stands for Data Zero Prohibited). However
we had the sense of the test inverted; fix this so that the
bit reads correctly.
To avoid this regressing the behaviou
Add support for HVC and SMC instructions to the A32 and
T32 decoder. Using these for real exceptions to EL2 or EL3
is currently not supported (the do_interrupt routine does
not handle them) but we require the instruction support to
implement PSCI.
Signed-off-by: Peter Maydell
Message-id: 14128650
tags/pull-target-arm-20141024
for you to fetch changes up to dbe9d1636787dd226d3f9a61c07fbc27e0db5bbf:
target-arm: A32: Emulate the SMC instruction (2014-10-24 12:19:15 +0100)
target-arm queue:
* remove pointless 'info pcmci
For the CPU type "any" (only used with linux-user) we were reporting
the L1Ip field as 0b00, which is reserved. Change this field to 0b10
instead, indicating a VIPT icache as the comment describes.
Reported-by: Laurent Desnogues
Signed-off-by: Peter Maydell
Reviewed-by: Laurent Desnogues
Messag
From: Fabian Aggeler
Make arm_current_el() return EL3 for secure PL1 and monitor mode.
Increase MMU modes since mmu_index is directly inferred from arm_
current_el(). Change assertion in arm_el_is_aa64() to allow EL3.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
Reviewed-by: Peter
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