Michael Tokarev writes:
> 15.11.2014 13:06, arei.gong...@huawei.com wrote:
>> From: Gonglei
>>
>> In this false branch, fd will leak when it is zero.
>> Change the testing condition.
>
> Why fd==0 is a concern here? It is a very unlikely
> situation that fd0 will be picked - firstly because
>
On Tue, Nov 18, 2014 at 07:03:58AM +0100, Paolo Bonzini wrote:
>
>
> On 17/11/2014 21:08, Michael S. Tsirkin wrote:
> > Add API to manage on-device RAM.
> > This looks just like regular RAM from migration POV,
> > but has two special properties internally:
> >
> > - block is sized on migrati
On 18/11/2014 05:26, Kevin O'Connor wrote:
> Support for PCI devices following the "SD Host Controller Simplified
> Specification Version 2.00" spec.
>
> Signed-off-by: Kevin O'Connor
> ---
> default-configs/pci.mak | 2 ++
> hw/sd/sdhci.c| 44 ++
On 17/11/2014 21:08, Michael S. Tsirkin wrote:
> Add API to manage on-device RAM.
> This looks just like regular RAM from migration POV,
> but has two special properties internally:
>
> - block is sized on migration, making it easier to extend
> without breaking migration compatibility
ping...
On 11/13/2014 09:10 AM, Gu Zheng wrote:
> This series is based on the previous patchset from Chen Fan:
> https://lists.nongnu.org/archive/html/qemu-devel/2014-05/msg02360.html
>
> We try to make cpu hotplug with device_add, and make
> "-device foo-x86_64-cpu" available，also we can set ap
On Mon, Nov 03, 2014 at 01:22:45PM +, Dr. David Alan Gilbert wrote:
> * David Gibson (da...@gibson.dropbear.id.au) wrote:
> > On Fri, Oct 03, 2014 at 06:47:22PM +0100, Dr. David Alan Gilbert (git)
> > wrote:
> > > From: "Dr. David Alan Gilbert"
> > >
> > > Open a return path, and handle mess
On Tue, Nov 04, 2014 at 10:19:15AM +, Dr. David Alan Gilbert wrote:
> * David Gibson (da...@gibson.dropbear.id.au) wrote:
> > On Fri, Oct 03, 2014 at 06:47:28PM +0100, Dr. David Alan Gilbert (git)
> > wrote:
> > > From: "Dr. David Alan Gilbert"
> > >
> > > QEMU_VM_CMD_PACKAGED is a migration
On Mon, Nov 03, 2014 at 03:53:03PM +0200, Cristian Klein wrote:
> On 03 Nov 2014, at 5:12 , David Gibson wrote:
>
> > On Fri, Oct 03, 2014 at 06:47:18PM +0100, Dr. David Alan Gilbert (git)
> > wrote:
> >> From: Cristian Klein
> >
> > This patch really, really requires a rationale in the commit
On Mon, Nov 03, 2014 at 06:59:35PM +, Dr. David Alan Gilbert wrote:
> * David Gibson (da...@gibson.dropbear.id.au) wrote:
> > On Fri, Oct 03, 2014 at 06:47:17PM +0100, Dr. David Alan Gilbert (git)
> > wrote:
> > > From: "Dr. David Alan Gilbert"
> > >
> > > The return path uses a non-blocking
On Mon, Nov 03, 2014 at 07:04:48PM +, Dr. David Alan Gilbert wrote:
> * David Gibson (da...@gibson.dropbear.id.au) wrote:
> > On Fri, Oct 03, 2014 at 06:47:16PM +0100, Dr. David Alan Gilbert (git)
> > wrote:
> > > From: "Dr. David Alan Gilbert"
> > >
> > > Postcopy needs a method to send mes
On Mon, Nov 17, 2014 at 07:07:33PM +, Dr. David Alan Gilbert wrote:
> * David Gibson (da...@gibson.dropbear.id.au) wrote:
> > On Fri, Oct 03, 2014 at 06:47:42PM +0100, Dr. David Alan Gilbert (git)
> > wrote:
> > > From: "Dr. David Alan Gilbert"
> > >
> > > On receiving MIG_RPCOMM_REQPAGES lo
On 17/11/2014 19:32, Peter Maydell wrote:
> On 17 November 2014 18:28, Ard Biesheuvel wrote:
>> This updates the Linux header to version 3.18-rc5, adding support for
>> (among other things) read-only memslots on ARM and arm64.
>>
>> Signed-off-by: Ard Biesheuvel
>
> So, to be clear, the idea i
On 11/17/2014 07:49 PM, Fam Zheng wrote:
> When which(1) is not installed, we complain "perl not found" because
> it's the first set_prog_path check. The error message is misleading.
>
> Fix it by adding a check for which(1) in the beginning.
Why not instead change set_prog_path to use 'command -
Support for PCI devices following the "SD Host Controller Simplified
Specification Version 2.00" spec.
Signed-off-by: Kevin O'Connor
---
default-configs/pci.mak | 2 ++
hw/sd/sdhci.c| 44
hw/sd/sdhci.h| 9 -
include/
The SDHCIClass defines a series of class "methods". However, no code
in the QEMU tree overrides these methods or even uses them outside of
sdhci.c.
Remove the virtual methods and replace them with direct calls to the
underlying functions. This simplifies the process of extending the
sdhci code t
Update the sdhci sysbus QOM types and methods so that sysbus is in
their name. This is in preparation for adding PCI versions of these
types and methods.
Signed-off-by: Kevin O'Connor
---
hw/sd/sdhci.c | 39 ---
hw/sd/sdhci.h | 6 +++---
2 files changed, 27
The Linux SDHCI PCI driver will only register the device if there is a
clock frequency set. So, set a default frequency of 52Mhz.
Signed-off-by: Kevin O'Connor
---
hw/sd/sdhci.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 55709da..
I'd like to be able to emulate SD cards on x86 machines for testing
purposes. I put together a patch series to modify the existing SDHCI
code so that it can also be used as a PCI device, and can thus be used
on any PCI platform (such as x86).
Vincent Palatin had patches to do this a couple of yea
Fix CP0.Config3.ISAOnExc write accesses on microMIPS processors. This
bit is mandatory for any processor that implements the microMIPS
instruction set. This bit is r/w for processors that implement both the
standard MIPS and the microMIPS instruction set. This bit is r/o and
hardwired to 1 if on
Include CP0.Config2 through CP0.Config5 registers in the register dump
produced with the `info registers' monitor command. Align vertically
with the registers already output.
Signed-off-by: Maciej W. Rozycki
---
Hi,
This proved useful in debugging a CP0.Config3.ISAOnExc problem, fixed
with
When which(1) is not installed, we complain "perl not found" because
it's the first set_prog_path check. The error message is misleading.
Fix it by adding a check for which(1) in the beginning.
Signed-off-by: Fam Zheng
---
tests/qemu-iotests/common.config | 2 ++
1 file changed, 2 insertions(+)
From: Gonglei
Reported-by:
https://bugs.launchpad.net/qemu/+bug/1393440
Signed-off-by: Gonglei
---
hw/pci/pcie.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c
index 58455bd..fbba589 100644
--- a/hw/pci/pcie.c
+++ b/hw/pci/pcie.c
@@ -145,7 +1
Stefan Hajnoczi writes:
> On Sun, Nov 02, 2014 at 10:37:59PM +0100, christoph.seif...@posteo.de wrote:
>> From: Christoph Seifert
>>
>> simpletrace.py does not recognize the tcg option while reading trace-events
>> file. In result simpletrace does not work on binary traces and tcg enabled
>> eve
On Mon, Nov 17, 2014 at 5:29 PM, Zhang Haoyu wrote:
>> Hi,
>>
>> I saw this page:
>>
>> http://www.linux-kvm.org/page/Migration.
>>
>> It looks like Migration is a feature provided by KVM? But when I look
>> at the Linux kernel source code, i.e., virt/kvm, and arch/x86/kvm, I
>> don't see the code
On 2014/11/18 0:25, Stefan Hajnoczi wrote:
> On Fri, Nov 07, 2014 at 08:42:57AM +0800, Gonglei wrote:
>> On 2014/11/7 1:26, Paolo Bonzini wrote:
>>
>>> On 06/11/2014 17:49, Stefan Hajnoczi wrote:
>> -Boot Devices Supporting dynamically modify boot order of
>> guest, and assuring taking eff
> Hi,
>
> I saw this page:
>
> http://www.linux-kvm.org/page/Migration.
>
> It looks like Migration is a feature provided by KVM? But when I look
> at the Linux kernel source code, i.e., virt/kvm, and arch/x86/kvm, I
> don't see the code for this migration feature.
>
Most of live migration code
Hi,
I saw this page:
http://www.linux-kvm.org/page/Migration.
It looks like Migration is a feature provided by KVM? But when I look
at the Linux kernel source code, i.e., virt/kvm, and arch/x86/kvm, I
don't see the code for this migration feature.
So I wonder where is the source code for the li
The other callers to blk_set_enable_write_cache() in this file
already check for s->blk == NULL.
Signed-off-by: Don Slutz
---
I think this is a bugfix that should be back ported to stable
releases.
I also think this should be done in xen's copy of QEMU for 4.5 with
back port(s) to active stable
The Load Vector Element Indexed and Store Vector Element Indexed
instructions compute an effective address in the usual manner.
However, they truncate that address to the natural boundary.
For example, the lvewx instruction will ignore the least significant
two bits of the address and thus load the
On 17 November 2014 20:08, Michael S. Tsirkin wrote:
> Add API to allocate on-device RAM.
> This looks just like regular RAM from migration POV,
> but has two special properties internally:
> - it is never exposed to guest
If it's not exposed to the guest why is it a MemoryRegion?
Those are pret
On Mon, Nov 17, 2014 at 10:08:53PM +0200, Michael S. Tsirkin wrote:
> Add API to manage on-device RAM.
> This looks just like regular RAM from migration POV,
> but has two special properties internally:
>
> - it is never exposed to guest
> - block is sized on migration, making it easier to
Use device rom API so we can painlessly extend ROMs in the
future. Note: migration is not affected, as we are
not actually allocating the RAM.
Use this in acpi: reserve x16 more RAM space.
Signed-off-by: Michael S. Tsirkin
---
hw/lm32/lm32_hwsetup.h | 3 ++-
include/hw/loader.h| 4 ++--
On Mon, Nov 17, 2014 at 10:08:46PM +0200, Michael S. Tsirkin wrote:
> At the moment we migrate ROMs which reside in fw cfg, which allows
> changing ROM code at will, and supports migrating largish blocks early,
> with good performance.
> However, we are running into a problem: changing size breaks
Add API to manage on-device RAM.
This looks just like regular RAM from migration POV,
but has two special properties internally:
- it is never exposed to guest
- block is sized on migration, making it easier to extend
without breaking migration compatibility or wasting
virtual
Add API to allocate on-device RAM.
This looks just like regular RAM from migration POV,
but has two special properties internally:
- it is never exposed to guest
- block is sized on migration, making it easier to extend
without breaking migration compatibility or wasting
virtual memory
Device is
If block length does not match, try to resize it.
Signed-off-by: Michael S. Tsirkin
---
arch_init.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/arch_init.c b/arch_init.c
index 593a990..bb30d01 100644
--- a/arch_init.c
+++ b/arch_init.c
@@ -1076,11 +1076,14 @
At the moment we migrate ROMs which reside in fw cfg, which allows
changing ROM code at will, and supports migrating largish blocks early,
with good performance.
However, we are running into a problem: changing size breaks
migration every time.
This already requires somewhat messy compatibility sup
simple wrapper so callers don't need to know about
dirty bitmap clients.
Signed-off-by: Michael S. Tsirkin
---
include/exec/ram_addr.h | 8
1 file changed, 8 insertions(+)
diff --git a/include/exec/ram_addr.h b/include/exec/ram_addr.h
index cf1d4c7..d7e5238 100644
--- a/include/exec/ra
hi everybody
No libvirt neither qemu mailing list could say, surely
developers will know thus..
I'd like to ask around if Xeon Phis are any good for
passthrough?
Are there any plans for near future or maybe there are
already some success stories using this product?
many thanks,
P.
On 13 November 2014 14:56, Peter Maydell wrote:
> The ARMv8 address translation system defines that a page table walk
> starts at a level which depends on the translation granule size
> and the number of bits of virtual address that need to be resolved.
> Where the translation granule is 64KB and
On 17 November 2014 17:08, Paolo Bonzini wrote:
> The following changes since commit c52e67924fbdadfa00668248f5c075542943c54c:
>
> Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into
> staging (2014-11-13 15:44:16 +)
>
> are available in the git repository at:
>
>
> git:
On 17 Nov 2014, at 14:35, Peter Maydell wrote:
> Compare the handling of 'rtc' and similar options: you get
> to have an "implied option name" so "-foo" is treated like
> "-foo enable=true",
I already considered this in a previous tentative version, but the
implementation doesn't work like thi
On 11/07/2014 10:16 AM, Vladimir Sementsov-Ogievskiy wrote:
from [PATCH v6 02/10]
+void qmp_block_dirty_bitmap_remove(const char *device, const char *name,
+ Error **errp)
+{
+BlockDriverState *bs;
+BdrvDirtyBitmap *bitmap;
+
+bs = bdrv_find(device
* David Gibson (da...@gibson.dropbear.id.au) wrote:
> On Fri, Oct 03, 2014 at 06:47:42PM +0100, Dr. David Alan Gilbert (git) wrote:
> > From: "Dr. David Alan Gilbert"
> >
> > On receiving MIG_RPCOMM_REQPAGES look up the address and
> > queue the page.
> >
> > Signed-off-by: Dr. David Alan Gilber
On 17 November 2014 19:32, Peter Maydell wrote:
> On 17 November 2014 18:28, Ard Biesheuvel wrote:
>> This updates the Linux header to version 3.18-rc5, adding support for
>> (among other things) read-only memslots on ARM and arm64.
>>
>> Signed-off-by: Ard Biesheuvel
>
> So, to be clear, the id
On 17 November 2014 18:28, Ard Biesheuvel wrote:
> This updates the Linux header to version 3.18-rc5, adding support for
> (among other things) read-only memslots on ARM and arm64.
>
> Signed-off-by: Ard Biesheuvel
So, to be clear, the idea is that this should go into 2.2 because
it (effectively
This updates the Linux header to version 3.18-rc5, adding support for
(among other things) read-only memslots on ARM and arm64.
Signed-off-by: Ard Biesheuvel
---
linux-headers/asm-arm/kvm.h | 2 ++
linux-headers/asm-arm64/kvm.h | 2 ++
linux-headers/asm-powerpc/kvm.h | 6 ++
linux-h
Hi,
On Wed, Feb 12, 2014 at 6:36 PM, Ian Main wrote:
> This is the sister command to blockdev-add. In Fam's example he uses
> the drive_del HMP command to clean up but it would be much nicer to
> have a way to do this via QMP.
Is there any news on this subject? It seems like we still need to
cl
On 13 November 2014 09:57, Claudio Fontana wrote:
> I agree with you that as a result of this discussion, the solution for QEMU
> upstreaming purposes needs to take everything discussed (possibly more)
> into account.
(Picking this email as a reasonable if slightly arbitrary
place to try to summa
On 17/11/2014 16:30, Max Reitz wrote:
> With all externally visible functions changed to use BlockBackend, this
> patch makes nbd use BlockBackend for everything internally as well.
>
> While touching them, substitute 512 by BDRV_SECTOR_SIZE in the calls to
> blk_read(), blk_write() and blk_co_d
On 17/11/2014 16:30, Max Reitz wrote:
> Because all BlockDriverStates behind a single BlockBackend reside in a
> single AioContext, it is fine to just pass these functions
> (blk_add_aio_context_notifier() and blk_remove_aio_context_notifier())
> through to the root BlockDriverState.
>
> Signed-of
On 15 November 2014 13:23, Mark Cave-Ayland
wrote:
> Hi Peter,
>
> This update fixes a regression with the interrupt mapping for SPARC64 which
> broke
> virtio. Please pull.
>
>
> ATB,
>
> Mark.
>
>
> The following changes since commit 4e70f9271dabc58fbf14680843bfac510c193152:
>
> Merge remote-
From: Gonglei
Function send_response(s, &qdict->base) returns a negative number
when any failures occured. But strerror()'s parameter cannot be
negative. Let's change the testing condition and pass '-ret' to
strerr().
Signed-off-by: Gonglei
Signed-off-by: Paolo Bonzini
---
qga/main.c | 4 ++--
Public bug reported:
hw/virtio/virtio-rng.c:150:31: warning: logical not is only applied to
the left hand side of comparison [-Wlogical-not-parentheses]
if (!vrng->conf.period_ms > 0) {
error_setg(errp, "'period' parameter expects a positive integer");
return;
}
Maybe bet
From: Gonglei
May pass freed pointer filename as an argument to error_report.
Signed-off-by: Gonglei
Signed-off-by: Paolo Bonzini
---
hw/mips/mips_mipssim.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/mips/mips_mipssim.c b/hw/mips/mips_mipssim.c
index 7ea0b9a..5d44c
From: Gonglei
In this false branch, fd will leak when it is zero.
Change the testing condition.
Signed-off-by: Gonglei
[Fix net_l2tpv3_cleanup as well. - Paolo]
Signed-off-by: Paolo Bonzini
---
net/l2tpv3.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/net/l2tpv3.c b
17.11.2014 18:52, Marc-André Lureau wrote:
> Nothing seems to be using functions from spice-experimental.h (better
> that way). Let's remove its inclusion.
Is it with current spice, or with some older spice too?
I mean, why this include has been added to start with -- was it
because of some featur
usb_ep_get and usb_handle_packet can deal with a NULL device, but we have
to avoid dereferencing NULL pointers when building the id.
Thanks to Gonglei for an initial stab at fixing this.
Signed-off-by: Paolo Bonzini
---
hw/usb/hcd-musb.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletion
On 17/11/2014 18:04, Michael S. Tsirkin wrote:
> acpi build modifies internal FW CFG RAM on first access
> but we forgot to mark it dirty.
> If this RAM has been migrated already, it won't be
> migrated again, returning corrupted tables to guest.
>
> Signed-off-by: Michael S. Tsirkin
> ---
> i
From: Gonglei
Signed-off-by: Gonglei
Signed-off-by: Paolo Bonzini
---
hw/pci/shpc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/pci/shpc.c b/hw/pci/shpc.c
index 65b2f51..9a39060 100644
--- a/hw/pci/shpc.c
+++ b/hw/pci/shpc.c
@@ -559,8 +559,9 @@ void shpc_device_hot
From: Gonglei
lseek will return -1 on error, g_malloc0(size) and read(,,size)
paramenters cannot be negative. We should add a check for return
value of lseek().
Signed-off-by: Gonglei
Signed-off-by: Paolo Bonzini
---
hw/core/loader.c | 13 +
1 file changed, 13 insertions(+)
diff
From: zhanghailiang
In function t_gen_mov_TN_preg and t_gen_mov_preg_TN, The begin check about the
validity of in-parameter 'r' is useless. We still access cpu_PR[r] in the
follow code if it is invalid. Which will be an out-of-bounds read error.
Fix it by using assert() to ensure it is valid bef
On 11/17/2014 09:14 AM, Max Reitz wrote:
>>> +-e '/^"QMP": {\s*$/, /^}\s*$/ c\' \
>> \s is a GNU sed extension. But we don't really need to care about
>> whitespace to the end of the line; I think that it is sufficient to just
>> match the following regex:
>>
>> -e '/^"QMP": {
From: Gonglei
Signed-off-by: Gonglei
Signed-off-by: Paolo Bonzini
---
qemu-char.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/qemu-char.c b/qemu-char.c
index bd0709b..4a76f0f 100644
--- a/qemu-char.c
+++ b/qemu-char.c
@@ -464,7 +464,7 @@ static const char * const mux_he
From: Gonglei
If 'i != index' for all acl->entries, variable
entry leaks the storage it points to.
Signed-off-by: Gonglei
Signed-off-by: Paolo Bonzini
---
util/acl.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/util/acl.c b/util/acl.c
index 938b7ae..571d686 1
acpi build modifies internal FW CFG RAM on first access
but we forgot to mark it dirty.
If this RAM has been migrated already, it won't be
migrated again, returning corrupted tables to guest.
Signed-off-by: Michael S. Tsirkin
---
include/hw/loader.h | 2 +-
hw/core/loader.c | 8 +---
From: Gonglei
Operands don't affect result (CONSTANT_EXPRESSION_RESULT)
((n->bar.aqa >> AQA_ASQS_SHIFT) & AQA_ASQS_MASK) > 4095
is always false regardless of the values of its operands.
This occurs as the logical second operand of '||'.
Signed-off-by: Gonglei
Signed-off-by: Paolo Bonzini
---
From: zhanghailiang
freeaddrinfo(result) does not assign result = NULL, after frees it.
There will be a double free when it goes error case.
It is reported by covertiy.
Reviewed-by: Gonglei
Cc: qemu-sta...@nongnu.org
Signed-off-by: zhanghailiang
Signed-off-by: Paolo Bonzini
---
net/l2tpv3.c
The following changes since commit c52e67924fbdadfa00668248f5c075542943c54c:
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
(2014-11-13 15:44:16 +)
are available in the git repository at:
git://github.com/bonzini/qemu.git tags/for-upstream
for you to fet
From: zhanghailiang
In function connect_to_qemu(), getaddrinfo() will allocate memory
that is stored into server, it should be freed by using freeaddrinfo()
before connect_to_qemu() return.
Cc: qemu-sta...@nongnu.org
Reviewed-by: Markus Armbruster
Signed-off-by: zhanghailiang
Signed-off-by: Pa
When EL3 is running in Aarch32 (or ARMv7 with Security Extensions)
VBAR has a secure and a non-secure instance, which are mapped to
VBAR_EL1 and VBAR_EL3.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
Reviewed-by: Peter Maydell
---
v8 -> v9
- Revert unnecessary CPreg definition ch
15.11.2014 13:06, arei.gong...@huawei.com wrote:
> From: Gonglei
>
> In this false branch, fd will leak when it is zero.
> Change the testing condition.
Why fd==0 is a concern here? It is a very unlikely
situation that fd0 will be picked - firstly because
fd0 is almost always open, and second -
From: Fabian Aggeler
When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
DFSR has a secure and a non-secure instance.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
Reviewed-by: Peter Maydell
---
v3 -> v4
- Reverted esr/dfsr back to array-based notation as a union
On Sat, Nov 15, 2014 at 06:06:44PM +0800, arei.gong...@huawei.com wrote:
> From: Gonglei
>
> Operands don't affect result (CONSTANT_EXPRESSION_RESULT)
> ((n->bar.aqa >> AQA_ASQS_SHIFT) & AQA_ASQS_MASK) > 4095
> is always false regardless of the values of its operands.
> This occurs as the logical
From: Fabian Aggeler
When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
DACR has a secure and a non-secure instance. Adds definition for DACR32_EL2.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
Reviewed-by: Peter Maydell
---
v8 -> v9
- Added definition for DACR
On Sat, Nov 15, 2014 at 06:06:40PM +0800, arei.gong...@huawei.com wrote:
> From: Gonglei
>
> In this false branch, fd will leak when it is zero.
> Change the testing condition.
>
> Signed-off-by: Gonglei
> ---
> net/l2tpv3.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by:
From: Fabian Aggeler
Adds secure and non-secure bank register suport for TTBCR.
Added new struct to compartmentalize the TCR data and masks. Removed old
tcr/ttbcr data and added a 4 element array of the new structs in cp15. This
allows for one entry per EL. Added a CP register definition for T
From: Fabian Aggeler
Add checks of SCR AW/FW bits when performing writes of CPSR. These SCR bits
are used to control whether the CPSR masking bits can be adjusted from
non-secure state.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
Reviewed-by: Peter Maydell
---
v10 -> v11
- Mo
On Fri, Nov 07, 2014 at 02:12:13PM +0100, Francesco Romani wrote:
Sorry for the long review delay. Looks pretty good, just one real issue
to think about at the bottom.
> +static void usage_threshold_disable(BlockDriverState *bs)
> +{
It would be safest to make this idempotent:
if (!usage_thres
From: Fabian Aggeler
Set ARM_FEATURE_EL3 feature for CPUs that implement Security Extensions.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
target-arm/cpu.c | 4
1 file changed, 4 insertions(+)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index d3db279..1871865 10064
On Mon, Nov 17, 2014 at 01:54:05PM +0800, zhanghailiang wrote:
> Signed-off-by: zhanghailiang
> ---
> net/socket.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Thanks, applied to my net tree:
https://github.com/stefanha/qemu/commits/net
Stefan
pgpcMVRH6k4NH.pgp
Description: PGP sig
Added CP register info entries for the ARMv7 MAIR0/1 secure banks.
Signed-off-by: Greg Bellows
Reviewed-by: Peter Maydell
---
v8 -> v9
- Added endianness support to the MAIR field structure definition.
v5 -> v6
- Changed _el field variants to be array based
---
target-arm/cpu.h| 21 +
Added CP register defintions for SDER and SDER32_EL3 as well as cp15.sder for
register storage.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
Reviewed-by: Peter Maydell
---
v8 -> v9
- Fixed declaration order of the SDER register components
v7 -> v8
From: Fabian Aggeler
When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
PAR has a secure and a non-secure instance.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
Reviewed-by: Peter Maydell
---
v8 -> v9
- Cleaned-up ats_write() to only call A32_BANKED_CURRENT_REG_
From: Fabian Aggeler
When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
IFAR and DFAR have a secure and a non-secure instance.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
Reviewed-by: Peter Maydell
---
v8 -> v9
- Reordered CP register component order
- Removed
From: Fabian Aggeler
SCR.{IRQ/FIQ} bits allow to route IRQ/FIQ exceptions to monitor CPU
mode. When taking IRQ exception to monitor mode FIQ exception is
additionally masked.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
Reviewed-by: Peter Maydell
--
From: Fabian Aggeler
When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
FCSEIDR, CONTEXTIDR, TPIDRURW, TPIDRURO and TPIDRPRW have a secure
and a non-secure instance.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
Reviewed-by: Peter Maydell
---
v8 -> v9
- Changed c
Version 11 of the ARM processor security extension (TrustZone) support. This
patchset includes changes to support the processor security extensions
on ARMv7 aarch32 with hooks for later enabling v8 aarch64/32.
This update includes minor fixes based on v9/v10 feedback. See the individual
patches
From: Fabian Aggeler
Adds secure and non-secure bank register suport for TTBR0 and TTBR1.
Changes include adding secure and non-secure instances of ttbr0 and ttbr1 as
well as a CP register definition for TTBR0_EL3. Added a union containing
both EL based array fields and secure and non-secure fie
From: Fabian Aggeler
Rename CSSELR (cache size selection register) and add secure
instance (AArch32).
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
Reviewed-by: Peter Maydell
---
v8 -> v9
- Replaced call to ARM_CP_SECSTATE_TEST with direct access
v7 -> v8
- Fix CSSELR CP regist
Added additional NS-bit to CPREG hash encoding. Updated hash lookup
locations to specify hash bit currently set to non-secure.
Signed-off-by: Greg Bellows
Reviewed-by: Peter Maydell
---
v8 -> v9
- Fixed CP_REG_NS_MASK
- Changed ENCODE_CP_REG argument order so ns follows is64
- Replaced use of
From: Fabian Aggeler
Use MVBAR register as exception vector base address for
exceptions taken to CPU monitor mode.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
Reviewed-by: Peter Maydell
---
v8 -> v9
- Fixed declaration order of the MVBARR registe
From: Fabian Aggeler
When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
IFSR has a secure and a non-secure instance. Adds IFSR32_EL2 definition and
storage.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
Reviewed-by: Peter Maydell
---
v8 -> v9
- Added definition
From: Fabian Aggeler
Implements NSACR register with corresponding read/write functions
for ARMv7 and ARMv8.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
Reviewed-by: Peter Maydell
---
v8 -> v9
- Removed unused NSACR constants
- Added TODO for trap
From: Fabian Aggeler
Prepare ARMCPRegInfo to support specifying two fieldoffsets per
register definition. This will allow us to keep one register
definition for banked registers (different offsets for secure/
non-secure world).
Also added secure state tracking field and flags. This allows for
i
From: Fabian Aggeler
Implements SCTLR_EL3 and uses secure/non-secure instance when
needed.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
Reviewed-by: Peter Maydell
---
v9 -> v10
- Fix SCTLR to use opc0 instead of cp
v8 -> v9
- Remove the v8 check in arm_cpu_reset when setting r
From: Fabian Aggeler
If EL3 is in AArch32 state certain cp registers are banked (secure and
non-secure instance). When reading or writing to coprocessor registers
the following macros can be used.
- A32_BANKED macros are used for choosing the banked register based on provided
input security ar
From: Sergey Fedorov
This patch is based on idea found in patch at
git://github.com/jowinter/qemu-trustzone.git
f3d955c6c0ed8c46bc0eb10b634201032a651dd2 by
Johannes Winter .
The TBFLAG captures the SCR NS secure state at the time when a TB is created so
the correct bank is accessed on system reg
From: Fabian Aggeler
Prepare for cp register banking by inserting every cp register twice,
once for secure world and once for non-secure world.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
Reviewed-by: Peter Maydell
---
v10 -> v11
- Fix indentation
v8 -> v9
- Fixed setting of
From: Fabian Aggeler
Define a new ARM CP register info list for the ARMv7 Security Extension
feature. Register that list only for ARM cores with Security Extension/EL3
support. Moving AArch32 SCR into Security Extension register group.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
1 - 100 of 202 matches
Mail list logo
